Intel Quark SE C1000, Platform Manual

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UART
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
32 Document Number: 334715-004EN
Table 13. UART Point-to-Point Topology Platform Routing Guidelines
UART
TXD, RXD, RTS, CTS SoC Breakout Main Routing
Transmission Line Segment TL0 TL1
Stackup Layer (Microstrip/
Stripline/Dual Stripline)
MS/SL MS/SL
Characteristic Impedance 50Ω +/- 10% 50Ω +/- 10%
Trace Width (w) 3.5 mils minimum Meet impedance
Min Trace Spacing (S1):
Between UART signals
4 mils 2W
Min Trace Spacing (S2):
Between UART signals and
other signals
5 mils 2W
Trace Segment Length <500 mil TL0+TL1 < 10000 mil
Total Trace Length <10000 mils
Reference VSS
Number of via allowed 3
6.2 Features
Both UART instances are configured identically. The following is a list of the UART
controller features:
 Operation compliant with the 16550 Standard
 Start bit
 5 to 8 bits of data
 Optional Parity bit (Odd or Even)
 1, 1.5, or 2 Stop bits
 Baud rate configurability between 300 baud and 2M baud
 Maximum baud rate is limited by system clock frequency divided by 16
 Supported baud rates: 300, 1200, 2400, 4800, 9600, 14400, 19200, 38400,
57600, 76800, 115200; multiples of 38.4 Kbps and multiples of 115.2 Kbps
up to 2M baud

Auto Flow Control mode as specified in the 16750 Standard
 Hardware Flow Control

Software Flow Control (when Hardware Flow Control is disabled)
 Hardware Handshake Interface to support DMA capability
 Interrupt Control
 FIFO support with 16B TX and RX FIFOs

Support of RS485
 Differential driver/receiver is external to the SoC

Driver enable (DE) and Receiver enable (RE) outputs are driven from the
SoC to control the differential driver/receiver