Intel PXA270, Optimization Manual

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Intel® PXA27x Processor Family Optimization Guide 2-7
Microarchitecture Overview
2.3 Intel® Wireless MMX™ Technology Pipeline
As the Intel® Wireless MMX™ Technology is tightly coupled with the Intel XScale®
Microarchitecture; the Intel® Wireless MMX™ Technology pipeline follows the similar pipeline
structure as the Intel XScale® Microarchitecture. Figure 2-2 shows the Intel® Wireless MMX™
Technology pipeline, which contains three independent pipeline threads:
•
X pipeline - Execution pipe
•
M pipeline - Multiply pipe
•
D pipeline - Memory pipe
2.3.1 Execute Pipeline Thread
2.3.1.1 ID Stage
The ID pipe stage is where decoding of Intel® Wireless MMX™ Technology instructions
commences. Because of the significance of the transit time from Intel XScale® Microarchitecture
in the ID pipe stage, only group decoding is performed in the ID stage, with the remainder of the
decoding being completed in the RF stage. However, it is worth noting that the register address
decoding is fully completed in the ID stage because the register file needs to be accessed at the
beginning of the RF stage.
All instructions are issued in a single cycle, and they pass through the ID stage in one cycle if no
pipeline stall occurs.
2.3.1.2 RF Stage
The RF stage controls the reading/writing of the register file, and determines if the pipeline has to
stall due to data or resource hazards. Instruction decoding also continues at the RF stage and
completes at the end of the RF stage. The register file is accessed for reads in the high phase of the
clock and accessed for writes in the low phase.If data or resource hazards are detected, the Intel®
Figure 2-2. Intel® Wireless MMX™ Technology Pipeline Threads and relation with Intel
XScale® Microarchitecture Pipeline
RF X1
X2 XWB
ID
M1 M2
D1 D2 DWB
X pipeline
M pipeline
D pipeline
MWB M3
IF1 IF2
ID RF
X1 X2 XWB
Intel
XScale®
Pipeline