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36

Evaluation Platform Board Manual

Intel

®

IQ80332 I/O Processor

Hardware Reference Section

3.7.2

JTAG Debug

The 80332 has a 20-pin JTAG connector (J7D2) that is in compliant with ARM Multi-ICE guidelines.

3.7.2.1

JTAG Port

Figure 9.

JTAG Port Pin-out

A9457-01

VTref

1

nTRST

3

TDI

5

TMS

7

TCK

9

RTCK

11

TDO

13

nSRST

15

DBGRQ

17

DBGACK 19

Vsupply

2

GND

4

GND

6

GND

8

GND

10

GND

12

GND

14

GND

16

GND

18

GND

20

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Summary of Contents for Processor IQ80332

Page 1: ...Intel IQ80332 I O Processor Evaluation Platform Board Manual September 2004 Document Number 274069 001US...

Page 2: ...OF ANY PROPOSAL SPECIFICATION OR SAMPLE Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification No license ex...

Page 3: ...Buckets 17 2 4 2 Contents of the Flash 17 2 5 Target Monitors 18 2 5 1 RedHat RedBoot 18 2 6 Host Communications Examples 19 2 6 1 Serial UART Communication 19 2 6 2 JTAG Debug Communication 19 2 6 3...

Page 4: ...Disable corresponding to signal name PBI_AD1141 3 9 6 4 6 Switch S7A1 6 Hot Plug Capable Disabled corresponding to signal name PBI_AD1541 3 9 6 4 7 Switch S7A1 7 SMBUS Manageability Address Bit 0 corr...

Page 5: ...xecutable File From Example Code 61 B 7 Running the Code Lab Debugger 62 B 7 1 Launching and Configuring Debugger 62 B 7 2 Manually Loading and Executing an Application Program 62 B 7 3 Displaying Sou...

Page 6: ...cation Example 20 5 Functional Block Diagram 25 6 Board Form Factor 26 7 Intel IQ80332 I O Processor Evaluation Platform Board Peripheral Bus Topology 31 8 Flash Connection on Peripheral Bus 32 9 JTAG...

Page 7: ...41 24 S7A1 4 PCI X Bus B Speed Enable Settings and Operation Mode 41 25 S7A1 5 PCI X Bus B Hot Plug Reset Disable Settings and Operation Mode 41 26 Switch S7A1 6 Hot Plug Capable Disabled Settings an...

Page 8: ...8 September 2004 Document Number 274069 001US Intel IQ80332 I O Processor Evaluation Platform Board Manual Contents Revision History Date Revision Description 27 September 2004 001 Initial Release...

Page 9: ...ntel 80332 I O Processor Datasheet 274066 Intel 80332 I O Processor Design Guide 273824 Intel 80332 I O Processor Specification Update 273927 Intel 80332 I O Processor JTAG Support White Paper 273963...

Page 10: ...com cgi bin morpheus home home jsp pSection LED AudioBuzzer DMT 1206 SMT Manufacturer RDI URL http www rdi electronics com products Audio DMT 1206 SMT html NVSRAM STK14C88 3 N 35 Manufacturer SIMTEK...

Page 11: ...hitecture and the company that licenses it CRB Customer Reference Board ICE In Circuit Emulator A piece of hardware used to mimic all the functions of a microprocessor IOP I O processor JTAG Joint Tes...

Page 12: ...6550 Compatible UARTs with flow control 4 pins Eight General Purpose Input Output GPIO Ports The 80332 is an integrated processor that addresses the needs of intelligent I O applications and helps red...

Page 13: ...Evaluation Platform Board Manual 13 Intel IQ80332 I O Processor Introduction Figure 1 Intel 80332 I O Processor Block Diagram 0 1 23 1 23 3 3...

Page 14: ...e Interposer Card may be used for the memory bus Information supplied separately Memory 256 MB 512 Mb x 16 DDRII SDRAM 400 MHz DIMM ECC Registered Onboard Power Board sources 1 25 V 2 5 V 3 3 V 5 V 12...

Page 15: ...s Be sure you are properly grounded before removing the board from the anti static bag 2 2 1 First Time Installation and Test For first time installation visually inspect the 80332 for any damage made...

Page 16: ...see Section 3 9 4 Connector Summary that is used to power the secondary PCI X slot This connector is compatible with a standard ATX hard drive power connector Caution Before connecting power to the en...

Page 17: ...package The kit also contains evaluation copies for several Software Development Tools These tools are for evaluation purposes and do not include any support Please contact the vendor directly for add...

Page 18: ...m s environment It can be used for both product development debug support and for end product deployment Flash and network booting Here are some highlights of RedBoot capabilities Boot scripting suppo...

Page 19: ...ptop computer but it is not necessary The host computer when loaded with the proper software can communicate with the board 2 6 2 JTAG Debug Communication Using a JTAG Emulator to communicate with the...

Page 20: ...unication Using a standard network connection the user can communicate with the board via the ethernet port Redboot also allows the user to remotely boot the platform using a BOOTP server through the...

Page 21: ...ools can be used Win32 using HyperTerminal UNIX using Kermit Linux using Minicom Solaris using Tip RedBoot Monitor startup Description terminal emulator runs on host and communicates with the board vi...

Page 22: ...Bits 8 Parity none Stop Bits 1 Flow Control none Start HyperTerminal Select Call from HyperTerminal panel Reset or power up 80332 board The Host screen reads For further information on the GDB Insight...

Page 23: ...debug information and symbols GDB set remotebaud 115200 Set baud rate for the 80332 Connect COM port When using Windows command prompt GDB target remote com1 Example screen output from board to host G...

Page 24: ...24 Evaluation Platform Board Manual Intel IQ80332 I O Processor Getting Started This Page Left Intentionally Blank...

Page 25: ...re 5 shows the functional block for the 80332 Figure 5 Functional Block Diagram DDR II 400 GPIOs DDR SDRAM Battery Backup 8 MB StrataFLASH JTAG Slot RS 232 I2C X8 Edge Connector HEX LED Buzzer Local B...

Page 26: ...as two serial ports and one RJ 45 Ethernet port The 80332 has one JTAG port compliant with ARM Multi ICE 20 pin connector standard The JTAG is targeted for the Intel XScale core and the CPLD and is us...

Page 27: ...umbers do not include the power required by a PCI X card mounted on the expansion slot Note The maximum current was calculated but not measured This numbers do not include the power required by a PCI...

Page 28: ...ata is read The IQ80332 features on board registered DDRII 400 MHz SDRAM arranged 512 Mbit x16 in density 256 MB and with ECC 3 4 1 1 Battery Backup Battery backup is provided to save any information...

Page 29: ...al Flash size is 8 MB 80332 Flash technology is based on Intel StrataFlash family 80332 Flash uses a 16 bit interface 80332 Flash utilizes the 80332 Peripheral Bus 80332 May be programmed using the PC...

Page 30: ...terrupt Routing to Intel 80332 I O Processor Interrupt System Resource HPI Temperature Sensor Header S_INTA PCI X Slot INTB Header S_INTB PCI X Slot INTC Header S_INTC PCI X Slot INTD Header S_INTD PC...

Page 31: ...Processor Evaluation Platform Board Peripheral Bus Topology Agilent HDSP A103Hex Display FLASH28F640J3C 16 bit 8Mb RDI DMT 1206 SMT AudioBuzzer XILINX XC9572XL 10TQ100C CPLD Grayhill HAB16W Rotary Swi...

Page 32: ...lash ROM Features Description Flash is an Intel StrataFlash technology Part number 28F640J3C Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 8 Figure 8 Flash Connection o...

Page 33: ...range is from CE86 0000 to CE86 FFFF in hex Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details 3 6 5 HEX Display The two pairs of Agilent HDSP A103 seven segment LEDs are...

Page 34: ...e details on addressing the CPLD Table 13 Battery Status Buffer Requirements BIT Read Write Name Description 0 R Battery Present 0 No backup battery 1 Battery backup is present 1 R Battery Charged 0 B...

Page 35: ...I O Processor Hardware Reference Section 3 7 Debug Interface 3 7 1 Console Serial Port The platform has two serial ports for debug purposes as described in Section 3 6 Intel IQ80332 I O Processor Eva...

Page 36: ...Debug The 80332 has a 20 pin JTAG connector J7D2 that is in compliant with ARM Multi ICE guidelines 3 7 2 1 JTAG Port Figure 9 JTAG Port Pin out A9457 01 VTref 1 nTRST 3 TDI 5 TMS 7 TCK 9 RTCK 11 TDO...

Page 37: ...I reset resets all devices on the board It occurs during the power up The SRST signal from the JTAG connector is a bi directional signal that can force a reset similar to the power up reset on the boa...

Page 38: ...et S7A1 1 APCI X Bus PCI XBus A Speed Set Closed S7A1 2 IOP RESET Sets IOP Reset Mode operation Open S7A1 3 IOP RETRY Sets IOP RETRY Mode operation Open S7A1 4 BPCI X Bus PCI X Bus B speed set Closed...

Page 39: ...Flash Enable Open J9D3 Buzzer Volume Open Table 18 Connector Summary Connector Description J1D1 RJ45 Network Connector for GbE NIC J1E1 RJ11 Dual Serial Port Connector J1L1 J1M1 J1M2 J1N1 J2M1 J2M2 SM...

Page 40: ...to signal name PBI_AD5 RESET MODE is latched at the de asserting edge of P_RST and it determines when the 80332 is held in reset until the Intel XScale core Reset bit is cleared in the PCI Configurat...

Page 41: ...his switch allows the user to enables or disable Hot Plug Reset on PCI X segment B Table 25 S7A1 5 PCI X Bus B Hot Plug Reset Disable Settings and Operation Mode 3 9 6 4 6 Switch S7A1 6 Hot Plug Capab...

Page 42: ...Switch S7A1 10 SMBUS Manageability Address Bit 1 corresponding to signal name PBI_AD16 This allows 80332 to address SMBus Slave Address 1 PBI_A16 Table 30 Switch S7A1 10 SMBUS Slave Address 0 Settings...

Page 43: ...Mode 1 2 Enables 16 bit Flash NC 8 bit Flash default mode Table 33 Jumper J1C1 Descriptions Jumper Description Factory Default J1C1 JTAG Chain Enable 1 2 Table 34 Jumper J1C1 Settings and Operation Mo...

Page 44: ...to EEPROM U7B2 Default Mode Pins 3 4 Connects SM_SDTA to EEPROM U7B2 Default Mode Pins 5 6 Connects SM_SCLK to GE_SMCLK for GBE control Pins 7 8 Connects SM_SDTA to GE_SMDAT for GBE control r Pins 9 1...

Page 45: ...n 8 table 34 for supported DDR333 and DDR II configurations For all registers relating to DRAM and other MCU related registers see the Intel 80332 I O Processor Developer s Manual 4 2 Components on th...

Page 46: ...Internal Bus By default address 0x0 is pointing to PCE0 where flash is located Currently the Intel Flash Recovery Utility FRU cannot be used with the IQ80332 An alternative to FRU would be to reprogr...

Page 47: ...memory re mapped CE80 0000 CE80 FFFF 64 KB 8 bit Product Code CE81 0000 CE81 FFFF 64 KB 8 bit Board Stepping CE24 0000 CE82 FFFF 64 KB 8 bit CPLD Firmware Revision CE83 0000 CE83 FFFF 64 KB 8 bit Disc...

Page 48: ...ory space for the 80332 before RedBoot boots Figure 13 Intel 80332 I O Processor Memory Map Peripheral Memory Mapped Registers I O Processor Reserved 0000 0000H ADDRESS FFFF FFFFH Reserved Address Spa...

Page 49: ...source code you may also go to the following location on the Intel site http developer intel com design intelxscale dev_tools 021022 index htm Virtual Address Physical Address Size MB Description 0x00...

Page 50: ...scrub ECC initialization code Initialization Sequence 1 Disable interrupts Technically they are disabled at reset but for soft reset this is included 2 Init PBIU Peripheral Bus Interface Unit chip sel...

Page 51: ...ttp www chips ibm com Interrupt Routing External interrupts are routed through the XINT pins on the 80332 Please see Table 9 for more details External interrupts are routed through the XINT pins on th...

Page 52: ...52 Evaluation Platform Board Manual Intel IQ80332 I O Processor IQ80321 and IQ80332 Comparisons This Page Left Intentionally Blank...

Page 53: ...evelopment tools and can begin working on new applications B 1 2 Necessary Hardware and Software This example uses the ATI Code Lab plug in for Microsoft Visual Studio the GNU Pro compiler the Macraig...

Page 54: ...Processor Getting Started and Debugger B 1 4 Related Web Sites Macraigor http www ocdemon net http developer intel com design intelxscale dev_tools 021022 index htm http developer intel com design iio...

Page 55: ...n the Raven can be found at the Macraigor web site Test software for the Raven is free and available for download at http www ocdemon net Merchant2 merchant mv Screen CTGY Store_Code MTS Category_C od...

Page 56: ...e under the program directory Note Do not install over an old version of ATI Code Lab When necessary uninstall Code Lab with Add Remove programs under the Control Panel before reinstalling To view the...

Page 57: ...rner of the Start Page window 5 The new project is now in the Solution Explorer window When this window is not open open it by View Solution Explorer 6 Right click on Project80332 and select Save Proj...

Page 58: ...bold Note that the assembler and the linker are invoked by GCC a Compiler path ToolDir BIN XSCALE ELF GCC EXE b Assembler path ToolDir BIN XSCALE ELF GCC EXE c Linker path ToolDir BIN XSCALE ELF GCC...

Page 59: ...e Software This Flash programmer only supports certain file formats Intel Hex Motorola srec and standard elf executable and linking format RedBoot s19 and RedBoot srec are both srec files TBD i32 is a...

Page 60: ...urns to the Connect window 6 Now press Connect Assembly code now visible 7 Select Memory Flash The OCDemon Flash Memory Programmer window appears 8 The Flash programmer needs a file which is architect...

Page 61: ...executed This requires that the source code is available and linked by the debugger to the executable code that is running on the evaluation board B 6 Building an Executable File From Example Code 1 L...

Page 62: ...toolbar icons Leave the mouse over the debug icons across the top on the toolbar to see a brief explanation of each 4 Click on the go icon and let RedBoot boot takes a minute until the RedBoot prompt...

Page 63: ...ny of these gray circles and a red dot appears The red dot represents a break point Single click the red dot to remove it or click the Remove all breakpoints icon Place a breakpoint on the following l...

Page 64: ...line in blink c 8 The animate icon can also be used to provide a Step Into effect that occurs at a specified time interval default of 1 second This can be modified in the Settings section of the View...

Page 65: ...ot be able to find the file B 8 3 Source Code The source code windows are opened by double clicking on the source files in the Workspace window under the files tab Viewing of mixed Assembly and C code...

Page 66: ...ecting Go To Memory Notice how the Memory window is brought up and the address contained in that register is shown Click on the registers tab Red means that the register value changed since the last f...

Page 67: ...constraints B 9 2 Hardware and Software Breakpoints The following section provides a brief overview of breakpoints See the Intel 80332 I O Processor Developer s Manual for more detailed information B...

Page 68: ...cution to a debug event handling routine The Intel 80200 processor debug architecture defines the following debug exceptions instruction breakpoint data breakpoint software breakpoint external debug b...

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