Specification Update
31
Errata
BG39.
Faulting Executions of FXRSTOR May Update State Inconsistently
Problem:
The state updated by a faulting FXRSTOR instruction may vary from one execution to
another.
Implication: Software that relies on x87 state or SSE state following a faulting execution of
FXRSTOR may behave inconsistently.
Workaround:Software handling a fault on an execution of FXRSTOR can compensate for execution
variability by correcting the cause of the fault and executing FXRSTOR again.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG40.
Performance Monitor Event EPT.EPDPE_MISS May Be Counted While EPT Is
Disabled
Problem:
Performance monitor event EPT.EPDPE_MISS (Event: 4FH, Umask: 08H) is used to
count Page Directory Pointer table misses while EPT (extended page tables) is enabled.
Due to this erratum, the processor will count Page Directory Pointer table misses
regardless of whether EPT is enabled or not.
Implication: Due to this erratum, performance monitor event EPT.EPDPE_MISS may report counts
higher than expected.
Workaround:Software should ensure this event is only enabled while in EPT mode.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG41.
Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
Problem:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication: If this erratum occurs the system may have unpredictable behavior including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the Intel 64 and IA-32 Intel
®
Architecture
Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
Intel has not observed this erratum with any commercially-available software or
system.
Workaround:Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status:
For the steppings affected, see the Summary Tables of Changes.
