LV Intel
®
Pentium
®
III Processor 512K Dual Processor Platform
Design Guide
35
5.4.2.2
Location of Bulk Decoupling
The location of bulk capacitance is not as critical as the high frequency decoupling components.
Careful placement is still important for these components to minimize the effects of parasitic board
impedances impacting transient response capability. Further, location and component impedances
are useful in simulation of the power conversion circuit. Bulk components should be placed close
to the processor sockets to minimize AC delays.
Note that bulk capacitors on voltage regulators are effectively electrically located behind the
inductance of the converter pins. As a result bulk capacitors need to be utilized close to the
processor socket.
The recommended number of bulk decoupling components and board load model for use with
voltage regulators is illustrated in Table 18 and Figure 19.
5.5
Recommendations
Intel recommends using simulation to design and verify LV Intel Pentium
III
processor 512K
systems. With the estimates provided in the previous section, a model of the power source, and the
model of the processor, system developers can begin analog modeling. The following sections
contain Intel’s design recommendations.
5.5.1
Decoupling Guidelines for LV Intel
®
Pentium
®
III Processor 512K
Designs
5.5.1.1
Decoupling Guidelines
The processor’s Micro-FCBGA package has eight surface mount decoupling capacitors. Six
0.68-µF capacitors are on V
CC
and two 0.68-µF capacitors are on V
TT
. In addition to the package
capacitors, sufficient board level capacitors are also necessary for power supply decoupling. These
guidelines are as follows:
•
High and Mid Frequency V
CC
decoupling – Place twenty-four 0.22-µF X5R 0603 capacitors
directly under the package on the solder side of the motherboard using at least two vias per
capacitor node. Ten 10-µF X7R 6.3V 1206-size ceramic capacitors should be placed around
the package periphery near the balls. Trace lengths to the vias should be designed to minimize
inductance. Avoid bending traces to minimize ESL.
•
High and Mid Frequency V
TT
decoupling – Place ten 1-µF X7R 0603 ceramic capacitors close
to the package. Via and trace guidelines are the same as above.
•
Bulk V
CC
decoupling – Minimum of 1200 µF capacitance with equivalent series resistance
less than or equal to 3.5 m
Ω.
Table 18. LV Intel Pentium
III
processor 512K Bulk Capacitance Recommendations
Design Type
Bulk Capacitance
ESR
ESL
RMS Current Rating
On-board design
4 OSCON, 560
µ
F
12 m
Ω
3.1 nH max
5.04 A rms
