Development Tools User’s Guide
285
Intel
®
IXP2400/IXP2800 Network Processors
Transactor States
A.8
Transactor States for PCI Pins
The transactor does not support tristate PCI pins. A pair of input and output signals are provided
for each corresponding PCI tristate pin to allow a foreign model to simulate the required
functionality of the PCI bus. A foreign model should deposit on the input pins using
XACT_set_state_value() and sample on the output pins using XACT_get_state_value() at the
appropriate cycles compliant to the PCI Specification. When an operation requires that any tristate
pin be no longer driven, the foreign model should deposit a value to its input signal corresponding
to the inactive state. Otherwise, the network processor will consider any pin with a previously
deposited active value to be asserted.
chip_name
.FC_TXCDAT
chip_name
.FC_TXCDAT_L
Output
Flow Control Engress data
chip_name
.FC_RXCDAT
chip_name
.FC_RXCDAT_L
Input
Flow Control Ingress data
chip_name
.FC_TXCSOF
chip_name
.FC_TXCSOF_L
Output
Flow Control Engress SOF (Start Of
Frame)
chip_name
.FC_RXCSOF
chip_name
.FC_RXCSOF_L
Input
Flow Control Ingress SOF
chip_name
.FC_TXCSRB
chip_name
.FC_TXCSRB_L
Output
Flow Control Engress SRB (Serialized
Ready Bits)
chip_name
.FC_RXCSRB
chip_name
.FC_RXCSRB_L
Input
Flow Control Ingress SRB
chip_name
.FC_TXCPAR
chip_name
.FC_TXCPAR_L
Output
Flow Control Engress Parity
chip_name
.FC_RXCPAR
chip_name
.FC_RXCPAR_L
Input
Flow Control Ingress Parity
chip_name
.FC_TXCFC
chip_name
.FC_TXCFC_L
Input
Flow Control Engress FIFO full
chip_name
.FC_RXCFC
chip_name
.FC_RXCFC_L
Output
Flow Control Ingress FIFO full
Table 2. IXP2800 Transactor States for QDR and MSF Pins (Continued) (Sheet 3 of 3)
Transactor State Names
Datasheet
Signal Name
I/O
Description
Table 3. IXP2400 Transactor States for PCI PIns (Sheet 1 of 2)
Transactor State Name
Datasheet
Signal Name
I/O
Description
chip_name.
PCI_CLK
PCI_CLK
input
Clock is being driven
by the simulator
chip_name
.pci_cluster.pci_pad_arch.bfm_read_PCI_ACK64_L
PCI_ACK64_L
output
chip_name
.pci_cluster.pci_pad_arch.bfm_write_PCI_ACK64_L
PCI_ACK64_L
input
chip_name
.pci_cluster.pci_pad_arch.bfm_read_PCI_AD_H
PCI_AD_H[63:0]
output