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Intel IXF1104, Datasheet

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Intel

®

 IXF1104 4-Port Gigabit Ethernet Media Access Controller

Datasheet

104

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

speed SerDes and are capable of operating in either an AC- or DC-coupled environment. AC 
coupling is recommended for this interface to ensure that the correct input bias current is supplied 
at the receiver.

The SerDes receive interface receives serialized data at 1.25 GHz. The interface is differential with 
two signals for the receive operation. The equalizer receives a differential signal that is equalized 
for the assumed media channel.

 

The SerDes transmit and receive interfaces are designed to operate 

within a 100 

Ω

 differential environment and all terminations are included on the device. The 

SerDes is capable of operating in either AC- or DC-coupled environments. 

5.6.2.1

Transmitter Operational Overview

The transmit section of the IXF1104 MAC has to serialize the Ten Bit Interface (TBI) data from the 
IXF1104 MAC MAC section and outputs this data at 1.25 GHz differential signal levels. The 
1.25 GHz differential SerDes signals are compliant with the Small Form Factor Pluggable (SFP) 
Multi-Source Agreement (MSA).

The transmitter section takes the contents of the data register within the MAC and synchronously 
transfers the data out, ten bits at a time – Least Significant Bit (LSB) first, followed by the next 
Most Significant Bit (MSB). When these ten bits have been serialized and transmitted, the next 
word of 10-bit data from the MAC is ready to be serialized for transmission.

The data is transmitted by the high-speed current mode differential SerDes output stage using an 
internal 1.25 GHz clock generated from the 125 MHz clock input. 

5.6.2.2

Transmitter Programmable Driver-Power Levels

The IXF1104 MAC SerDes core has programmable transmitter power levels to enhance usability 
in any given application.The SerDes Registers are programmable to allow adjustment of the 
transmit core driver output power. When driving a 100 

Ω

 differential terminated network, these 

output power settings effectively establish the differential voltage swings at the driver output.

The 

“TX Driver Power Level Ports 0 - 3 ($0x784)"

 allows the selection of four discrete power 

settings. The selected power setting of these inputs is applied to each of the transmit core drivers on 
a per-port basis. 

Table 29 “SerDes Driver TX Power Levels”

 lists the

 

normalized power settings of 

the transmit drivers as a function of the Driver Power Control inputs. The normalized current 
setting is 10 mA, which corresponds to the normalized power setting of 1.0. This is the default 
setting of the IXF1104 MAC SerDes interface. Other values listed in the Normalized Driver Power 
Setting column are multiples of 10 mA. For example, with inputs at 1110, the driver power is the 
following:

.5 x 10 mA = 5 mA.

Table 29.  SerDes Driver TX Power Levels

DRVPWRx[3]

DRVPWRx[2]

DRVPWRx[1]

DRVPWRx[0]

Normalized 

Driver Power 

Setting

Driver Power

0

0

1

1

1.33

13.3 mA

NOTE: All other values are reserved.

Summary of Contents for IXF1104

Page 1: ...face supports data transfers up to 4 Gbps in both modes 32 bit Multi PHY mode 133 MHz 4 x 8 bit Single PHY mode 125 MHz IEEE 802 3 compliant Flow Control Loss less up to 9 6 KB packets and 5 km links Jumbo frame support for 9 6 KB packets Internal per channel FIFOs 32 KB Rx 10 KB Tx Flexible 32 16 8 bit CPU interface Programmable Packet handling Filter broadcast multicast unicast VLAN and errored ...

Page 2: ...without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The IXF1104 MAC Media Access Controller may contain design defects or errors known as errata which may cause...

Page 3: ...lexed Ball Connections 58 4 5 2 SPI3 MPHY SPHY Ball Connections 59 4 6 Ball State During Reset 61 4 7 Power Supply Sequencing 63 4 7 1 Power Up Sequence 63 4 7 2 Power Down Sequence 63 4 8 Pull Up Pull Down Ball Guidelines 64 4 9 Analog Power Filtering 64 5 0 Functional Descriptions 66 5 1 Media Access Controller MAC 66 5 1 1 Features for Fiber and Copper Mode 67 5 1 1 1 Padding of Undersized Fram...

Page 4: ...iming SPHY 88 5 2 2 9 SPI3 Flow Control 91 5 2 3 Pre Pending Function 93 5 3 Gigabit Media Independent Interface GMII 93 5 3 1 GMII Signal Multiplexing 94 5 3 2 GMII Interface Signal Definition 94 5 4 Reduced Gigabit Media Independent Interface RGMII 96 5 4 1 Multiplexing of Data and Control 96 5 4 2 Timing Specifics 97 5 4 3 TX_ER and RX_ER Coding 97 5 4 3 1 In Band Status 99 5 4 4 10 100 Mbps Fu...

Page 5: ... LED Interface 115 5 8 1 Modes of Operation 115 5 8 2 LED Interface Signal Description 116 5 8 3 Mode 0 Detailed Operation 116 5 8 4 Mode 1 Detailed Operation 117 5 8 5 Power On Reset Initialization 118 5 8 6 LED DATA Decodes 118 5 8 6 1 LED Signaling Behavior 119 5 9 CPU Interface 120 5 9 1 Functional Description 121 5 9 1 1 Read Access 121 5 9 1 2 Write Access 121 5 9 1 3 CPU Timing Parameters 1...

Page 6: ...iming 145 7 6 2 MDC Low Speed Operation Timing 145 7 6 3 MDIO AC Timing 146 7 7 Optical Module and I2 C AC Timing Specification 147 7 7 1 I2 C Interface Timing 147 7 8 CPU AC Timing Specification 149 7 8 1 CPU Interface Read Cycle AC Timing 149 7 8 2 CPU Interface Write Cycle AC Timing 149 7 9 Transmit Pause Control AC Timing Specification 151 7 10 JTAG AC Timing Specification 152 7 11 System AC T...

Page 7: ...11 MPHY Transmit Logical Timing 85 12 MPHY Receive Logical Timing 86 13 MPHY 32 Bit Interface 86 14 SPHY Transmit Logical Timing 88 15 SPHY Receive Logical Timing 89 16 SPHY Connection for Two Intel IXF1104 MAC Ports 8 Bit Interface 90 17 MAC GMII Interconnect 94 18 RGMII Interface 96 19 TX_CTL Behavior 98 20 RX_CTL Behavior 98 21 Management Frame Structure Single Frame Format 101 22 MDI State 102...

Page 8: ... 229 60 Ordering Information Sample 230 Tables 1 Ball List in Alphanumeric Order by Signal Name 24 2 Ball List in Alphanumeric Order by Ball Location 30 3 SPI3 Interface Signal Descriptions 39 4 SerDes Interface Signal Descriptions 47 5 GMII Interface Signal Descriptions 48 6 RGMII Interface Signal Descriptions 50 7 CPU Interface Signal Descriptions 51 8 Transmit Pause Control Interface Signal Des...

Page 9: ...rs 140 48 RGMII Interface Timing Parameters 141 49 GMII 1000BASE T Transmit Signal Parameters 142 50 GMII 1000BASE T Receive Signal Parameters 143 51 SerDes Timing Parameters 144 52 MDIO Timing Parameters 146 53 I2 C AC Timing Characteristics 147 54 CPU Interface Write Cycle AC Signal Parameters 150 55 Transmit Pause Control Interface Timing Parameters 151 56 JTAG AC Timing Parameters 152 57 Syste...

Page 10: ...0x60 181 96 PHY Status Port Index 0x61 182 97 PHY Identification 1 Port Index 0x62 183 98 PHY Identification 2 Port Index 0x63 184 99 Auto Negotiation Advertisement Port Index 0x64 184 100 Auto Negotiation Link Partner Base Page Ability Port Index 0x65 185 101 Auto Negotiation Expansion Port Index 0x66 186 102 Auto Negotiation Next Page Transmit Port Index 0x67 187 103 Port Enable 0x500 188 104 In...

Page 11: ...0x61F 207 137 TX FIFO Port Reset 0x620 207 138 TX FIFO Overflow Frame Drop Counter Ports 0 3 0x621 0x624 208 139 TX FIFO Errored Frame Drop Counter Ports 0 3 0x625 0x629 209 140 TX FIFO Occupancy Counter for Ports 0 3 0x62D 0x630 210 141 TX FIFO Port Drop Enable 0x63D 210 142 MDIO Single Command 0x680 211 143 MDIO Single Read and Write Data 0x681 211 144 Autoscan PHY Address Enable 0x682 212 145 M...

Page 12: ... Grid Array CBGA compliant with RoHS and Product Ordering Number information 55 Modified Table 12 JTAG Interface Signal Descriptions changed Standard to 3 3 V LVTTL from 2 5 V CMOS 72 Modified Figure 9 PAUSE Frame Format changed Preamble byte count to 7 bytes 85 Modified Figure 11 MPHY Transmit Logical Timing updated TDAT 31 0 86 Modified Figure 12 MPHY Receive Logical Timing updated RDAT 31 0 88 ...

Page 13: ...egister and register default value 186 Modified Table 101 Auto Negotiation Expansion Port Index 0x66 added Need one sentence descriptions of register and register default value 187 Modified Table 102 Auto Negotiation Next Page Transmit Port Index 0x67 added Need one sentence descriptions of register and register default value 211 Modified Table 143 MDIO Single Read and Write Data 0x681 changed MDI...

Page 14: ...1 AD2 AD3 AD22 AD23 AD24 from NC to No Ball 30 Modified Table 2 Ball List in Alphanumeric Order by Ball Location Changed A10 from VCC to VDD Changed C12 form VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD Changed Ball A1 from NC to No Pad Changed Balls A2 A3 A22 A23 A24 B1 B2 B23 B24 C1 C24 AB1 AB24 AC1 AC2 AC23 AC24 AD1 AD2 AD3 AD22 AD23 AD24 from NC to No Ball 38 Updated Figu...

Page 15: ...w Section 5 1 1 3 6 Filter CRC Error Packets 69 Added note under Table 22 CRC Errored Packets Drop Enable Behavior 69 Added new Section 5 1 2 Flow Control including Figure 7 Packet Buffering FIFO Figure 8 Ethernet Frame Format and Figure 9 PAUSE Frame Format 73 Replaced Section 5 1 2 1 5 Transmit Pause Control Interface added Table 23 Valid Decodes for TXPAUSEADD 2 0 and modified Table 10 Transmit...

Page 16: ...changed links under Description to Link LED Enable 0x502 NA Removed old Figure 30 CPU External and Internal Connections 123 Modified Table 37 Byte Swapper Behavior edited added new values 123 Modified second paragraph under Section 5 10 TAP Interface JTAG 126 Modified Figure 33 SPI3 Interface Loopback Path 126 Added note under Section 5 11 2 Line Side Interface Loopback 127 Modified Figure 34 Line...

Page 17: ...14 13 12 171 Modified Table 90 Diverse Config Write Port_Index 0x18 edited description and type for bits 18 8 changed bits 3 1 to Reserved added table note 2 172 Renamed modified Table 91 RX Packet Filter Control Port_Index 0x19 old register name added RX to heading added table note 2 174 Modified Table 93 MAC RX Statistics Port_Index 0x20 0x39 added note to RxPauseMacControlReceivedCounter descri...

Page 18: ... Section 8 4 11 Optical Module Register Overview 222 Modified Table 153 Optical Module Status Ports 0 3 0x799 edited register description 222 Modified Table 154 Optical Module Control Ports 0 3 0x79A changed register description NA Removed Reserved Table 190 TX and RX AC DC Coupling Selection 7x780 NA Deleted old Figure 19 Typical GBIC Module Functional Diagram under Section 5 7 Optical Module Int...

Page 19: ...Definitions Addr 0x5B8 172 Added Table 100 RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions Addr 0x5B9 172 Added Table 101 RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions Addr 0x5BA 172 Added Table 102 RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions Addr 0x5BB 178 Modified Table 110 TX FIFO Number of Dropped Packets Register Ports 0 3 Addr 0x625 0x629 177 Modified Tabl...

Page 20: ...on 5 0 Functional Descriptions on page 66 gives detailed information about the operation of the IXF1104 including general features and interface types and descriptions Section 7 0 Electrical Specifications on page 132 provides information on the product operating parameters electrical specifications and timing parameters Section 8 0 Register Set on page 155 illustrates and lists the memory map det...

Page 21: ...twork processor is supported through a System Packet Interface Phase 3 SPI3 media interface The following PHY interfaces are selected on a per port basis Serializer Deserializer SerDes with Optical Module Interface support Gigabit Media Independent Interface GMII Reduced Gigabit Media Independent Interface RGMII Figure 1 illustrates the IXF1104 MAC block diagram Figure 1 Block Diagram Forwarding E...

Page 22: ...al Architecture SPI3 Interface CPU Interface RMON Statistics Packet TX Buffer RX Packet Buffer Packet Buffer Packet Buffer Clock Control Block Clock Register Block PLLs MDIO OMI TX TX TX RX RX RX 10 100 1000 MAC 10 100 1000 MAC 10 100 1000 MAC 10 100 1000 MAC RGMII GMII Interface RGMII GMII Interface RGMII GMII Interface RGMII GMII Interface PMA Layer SerDes PMA Layer SerDes PMA Layer SerDes PMA L...

Page 23: ...3 J24 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C2...

Page 24: ...er mode Table 1 Ball List in Alphanumeric Order by Signal Name Signal Name Ball Location AVDD1P8_1 A5 AVDD1P8_1 A20 AVDD1P8_2 T23 AVDD1P8_2 AB16 AVDD2P5_1 AD20 AVDD2P5_2 R18 AVDD2P5_2 U14 CLK125 AD19 COL_01 AB6 COL_11 AB10 COL_21 AD15 COL_31 AB17 CRS_01 AA5 CRS_11 AA9 CRS_21 AB15 CRS_31 AC16 DTPA_02 D3 DTPA_12 L1 DTPA_22 A9 DTPA_32 J7 GND B6 GND B10 GND B15 GND B19 GND D4 GND D8 GND D12 GND D13 GN...

Page 25: ...I2 C_CLK L23 I2 C_DATA_03 L24 I2 C_DATA_13 M24 I2 C_DATA_23 N24 I2 C_DATA_33 P24 LED_CLK K24 LED_DATA M22 LED_LATCH L22 MDC4 W24 MDIO4 V21 MOD_DEF_INT N22 NC D24 NC E12 NC F11 NC G15 NC H7 NC H18 NC J21 NC K7 NC K18 NC K20 NC K22 NC L18 NC L19 NC L21 NC M7 NC M18 NC M20 NC N3 NC N18 NC P2 NC P4 NC P6 NC P7 NC P8 NC P17 Signal Name Ball Location NC P18 NC R5 NC R10 NC R12 NC R13 NC R15 NC R20 NC T6...

Page 26: ...24 RDAT_312 F24 RENB_02 A13 RENB_12 A18 RENB_22 C19 RENB_32 E24 REOP_02 C16 REOP_12 D18 REOP_22 C23 REOP_32 J19 RERR_02 A16 RERR_12 G17 RERR_22 D20 RERR_32 H20 RFCLK2 A19 RMOD02 G14 RMOD12 G13 RPRTY_02 E15 RPRTY_12 G16 RPRTY_22 E20 RPRTY_32 F20 RSOP_02 B16 RSOP_12 C18 RSOP_22 E23 RSOP_32 J18 RSX2 E13 RVAL_02 C15 RVAL_12 B18 RVAL_22 E19 RVAL_32 F22 RX_DV_01 V5 RX_DV_11 AB11 RX_DV_21 Y24 RX_DV_31 V1...

Page 27: ...T282 G8 TDAT292 G9 TDAT302 F5 TDAT312 F7 TDI J24 TDO H24 TENB_02 B7 TENB_12 E2 TENB_22 C9 TENB_32 J4 TEOP_02 A7 TEOP_12 F3 TEOP_22 E4 TEOP_32 H5 TERR_02 A8 TERR_12 K1 TERR_22 E11 TERR_32 J8 TFCLK2 D7 TMOD02 A6 TMOD12 D9 TMS H22 TPRTY_02 D5 TPRTY_12 G3 TPRTY_22 B9 TPRTY_32 J6 TRST_L J23 TSOP_02 C7 TSOP_12 E3 TSOP_22 C10 TSOP_32 J5 TSX E1 Signal Name Ball Location TX_EN_01 AB2 TX_EN_11 Y8 TX_EN_21 A...

Page 28: ...n UPX_DATA5 N5 UPX_DATA6 M5 UPX_DATA7 K5 UPX_DATA8 P5 UPX_DATA9 L6 UPX_DATA10 L7 UPX_DATA11 N7 UPX_DATA12 L8 UPX_DATA13 H9 UPX_DATA14 J9 UPX_DATA15 N10 UPX_DATA16 M10 UPX_DATA17 K10 UPX_DATA18 G10 UPX_DATA19 H11 UPX_DATA20 G11 UPX_DATA21 K12 UPX_DATA22 G12 UPX_DATA23 K13 UPX_DATA24 H14 UPX_DATA25 K15 UPX_DATA26 N15 UPX_DATA27 M15 UPX_DATA28 J16 UPX_DATA29 H16 UPX_DATA30 J17 UPX_DATA31 L17 UPX_RD_L...

Page 29: ... VDD2 M12 VDD3 B13 VDD3 B17 VDD3 B21 VDD3 D23 VDD3 F13 VDD3 F17 VDD3 H19 VDD3 H23 VDD3 J13 VDD3 M13 VDD3 M16 VDD3 M19 VDD3 M23 VDD4 N13 VDD4 N16 VDD4 N19 VDD4 N23 VDD4 T13 VDD4 U19 VDD4 U23 VDD4 W13 VDD4 W17 VDD4 AA23 VDD4 AC13 VDD4 AC17 VDD4 AC21 VDD5 N2 VDD5 N6 VDD5 N9 Signal Name Ball Location VDD5 N12 VDD5 T12 VDD5 U2 VDD5 U6 VDD5 W8 VDD5 W12 VDD5 AA2 VDD5 AC4 VDD5 AC8 VDD5 AC12 Signal Name Ba...

Page 30: ...No Ball B2 No Ball B3 TDAT02 B4 VDD2 B5 TDAT62 B6 GND B7 TENB_02 B8 VDD2 B9 TPRTY_22 B10 GND B11 PTPA2 B12 VDD2 B13 VDD3 B14 RDAT_22 B15 GND B16 RSOP_02 B17 VDD3 B18 RVAL_12 B19 GND B20 RDAT_162 B21 VDD3 B22 RDAT_172 B23 No Ball B24 No Ball C1 No Ball C2 TDAT12 C3 TDAT22 C4 TDAT42 C5 TDAT52 C6 TDAT72 C7 TSOP_02 C8 TDAT232 C9 TENB_22 C10 TSOP_22 C11 STPA2 C12 VDD C13 RDAT_42 C14 RDAT_32 C15 RVAL_02...

Page 31: ...DAT_312 G1 TDAT92 G2 TDAT102 G3 TPRTY_12 G4 TDAT242 G5 TDAT252 G6 TDAT262 G7 TDAT272 G8 TDAT282 G9 TDAT292 G10 UPX_DATA18 G11 UPX_DATA20 G12 UPX_DATA22 G13 RMOD12 G14 RMOD02 G15 NC G16 RPRTY_12 G17 RERR_12 G18 RDAT_242 G19 RDAT_252 G20 RDAT_262 G21 RDAT_272 G22 RDAT_282 G23 RDAT_292 G24 RDAT_302 H1 TDAT112 H2 VDD2 H3 TDAT152 H4 GND H5 TEOP_32 H6 VDD2 H7 NC H8 GND H9 UPX_DATA13 Ball Location Signal...

Page 32: ... VDD L17 UPX_DATA31 L18 NC L19 NC L20 GND L21 NC L22 LED_LATCH L23 I2 C_CLK L24 I2 C_DATA_03 M1 UPX_RDY_L M2 VDD2 M3 UPX_DATA3 M4 GND M5 UPX_DATA6 M6 VDD2 M7 NC M8 GND M9 VDD2 M10 UPX_DATA16 M11 GND M12 VDD2 M13 VDD3 M14 GND M15 UPX_DATA27 M16 VDD3 M17 GND M18 NC M19 VDD3 M20 NC M21 GND M22 LED_DATA M23 VDD3 M24 I2 C_DATA_13 N1 UPX_ADD1 N2 VDD5 N3 NC Ball Location Signal Name N4 GND N5 UPX_DATA5 N...

Page 33: ...DD T12 VDD5 T13 VDD4 T14 VDD T15 GND T16 RXD4_31 T17 RXD5_31 T18 RXD6_31 T19 RXD7_31 T20 TXPAUSEFR T21 NC T22 NC T23 AVDD1P8_2 T24 RX_P_23 U1 UPX_ADD5 U2 VDD5 U3 UPX_ADD9 U4 GND U5 NC U6 VDD5 U7 NC U8 GND U9 NC U10 VDD U11 NC U12 GND U13 GND U14 AVDD2P5_2 U15 VDD U16 UPX_WIDTH0 U17 GND U18 NC U19 VDD4 U20 RX_ER_31 U21 GND Ball Location Signal Name U22 RX_N_13 U23 VDD4 U24 RX_P_33 V1 UPX_ADD6 V2 UP...

Page 34: ...4_11 AA8 GND AA9 CRS_11 AA10 VDD AA11 RXD6_11 AA12 GND AA13 GND AA14 TXD4_31 AA15 VDD AA16 TXD6_31 AA17 GND AA18 TXD7_21 AA19 VDD AA20 TXD6_21 AA21 GND AA22 RX_ER_21 AA23 VDD4 AA24 RXC_21 AB1 No Ball AB2 TX_EN_01 AB3 TXD4_01 AB4 TXD6_01 AB5 RXD6_01 AB6 COL_01 AB7 TXD1_11 AB8 TXD5_11 AB9 TXD2_11 AB10 COL_11 AB11 RX_DV_11 AB12 GND AB13 TX_ER_31 AB14 TXC_31 AB15 CRS_21 Ball Location Signal Name AB16 ...

Page 35: ...on Number 009 Revision Date 27 Oct 2005 AD6 TX_ER_11 AD7 TXC_11 AD8 TXD6_11 AD9 TXD3_11 AD10 RXD4_11 AD11 RXC_11 AD12 SYS_RST_L AD13 TX_P_13 AD14 TX_N_13 AD15 COL_21 AD16 TXD4_21 AD17 TX_ER_21 AD18 TX_N_33 AD19 CLK125 AD20 AVDD2P5_1 AD21 GND AD22 No Ball AD23 No Ball AD24 No Ball Ball Location Signal Name ...

Page 36: ...Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller 36 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 ...

Page 37: ...Signal Mnemonic followed by a bracketed serial designation For example the set of 11 CPU Address Bus signals is identified as UPX_ADD 10 0 Port Designation Individual signals that apply to a particular port are designated by the Signal Mnemonic immediately followed by an underscore and the Port Designation For example RGMII Transmit Control signals are identified as TX_CTL_0 TX_CTL_1 TX_CTL_2 and ...

Page 38: ...BLE_0 3 TX_FAULT_0 3 RX_LOS_0 3 TX_FAULT_INT RX_LOS_INT MOD_DEF_INT I2 C_CLK I2 C_DATA_0 3 SPI3 Interface JTAG Interface MDIO Interface Pause Control Interface CPU Interface LED Interface System Interface GMII RGMII GMII and RGMII Interfaces Data and clock balls are shared for GMII and RGMII Interfaces SerDes Interface Optical Module Interface Signals These optical module signals are multiplexed o...

Page 39: ...T5_2 TDAT4_2 TDAT3_2 TDAT2_2 TDAT1_2 TDAT0_2 C8 F9 E10 E9 E8 E7 E6 E5 Input 3 3 V LVTTL Transmit Data Bus Carries payload data to the IXF1104 MAC egress path Mode 32 bit Multi PHY 4 x 8 Single PHY Bits 23 16 7 0 for port 2 TDAT15 TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 TDAT9 TDAT8 TDAT7_1 TDAT6_1 TDAT5_1 TDAT4_1 TDAT3_1 TDAT2_1 TDAT1_1 TDAT0_1 H3 J3 J2 J1 H1 G2 G1 F1 Input 3 3 V LVTTL Transmit Data Bus...

Page 40: ...ated control and status signals TERR_0 TERR_0 TERR_1 TERR_2 TERR_3 A8 K1 E11 J8 Input 3 3 V LVTTL Transmit Error TERR indicates that there is an error in the current packet TERR is valid when simultaneously asserted with TEOP and TENB 32 bit Multi PHY mode TERR_0 is the bit asserted for all 32 bits 4 x 8 Single PHY mode Each bit of TERR_0 3 corresponds to the respective TDAT 3 0 _n channel TSOP_0 ...

Page 41: ...ust be asserted simultaneously for TMOD 1 0 to be valid 4 x 8 Single PHY mode MOD 1 0 is not required TSX NA E1 Input 3 3 V LVTTL Transmit Start of Transfer 32 bit Multi PHY mode TSX asserted with TENB 1 indicates that the PHY address is present on TDAT 7 0 The valid values on TDAT 7 0 are 3 2 1 and 0 When TENB 0 TSX is not used by the PHY device NOTE Only TDAT 1 0 are relevant all other bits are ...

Page 42: ...utput 3 3 V LVTTL Selected PHY Transmit Packet Available STPA is only meaningful in a 32 bit multi PHY mode STPA is a direct status indication for transmit FIFOs of ports 0 3 When High STPA indicates that the amount of data in the TX FIFO specified by the latest in band address is below the TX FIFO High watermark When the High watermark is crossed STPA transitions Low to indicate the TX FIFO is al...

Page 43: ...ess on TADR is sampled by the PHY device PTPA is updated on the rising edge of TFCLK RDAT31 RDAT30 RDAT29 RDAT28 RDAT27 RDAT26 RDAT25 RDAT24 RDAT7_3 RDAT6_3 RDAT5_3 RDAT4_3 RDAT3_3 RDAT2_3 RDAT1_3 RDAT0_3 F24 G24 G23 G22 G21 G20 G19 G18 Output 3 3 V LVTTL Receive Data Bus RDAT carries payload data and in band addresses from the IXF1104 MAC Mode 32 bit Multi PHY 4 x 8 Single PHY Bits 31 24 7 0 for ...

Page 44: ...HY mode RPRTY_0 is the parity bit for all 32 bits 4 x 8 Single PHY mode Each bit of RPRTY_0 3 corresponds to the respective RDAT 3 0 _n channel RENB_0 RENB_0 RENB_1 RENB_2 RENB_3 A13 A18 C19 E24 Input 3 3 V LVTTL Receive Read Enable The RENB signal controls the flow of data from the receive FIFOs During data transfer RVAL must be monitored as it indicates if the RDAT 31 0 RPRTY RMOD 1 0 RSOP REOP ...

Page 45: ...ta signals RVAL is Low between transfers and assertion of RSX It is also Low when the IXF1104 MAC pauses a transfer due to an empty receive FIFO When a transfer is paused by holding RENB High RVAL holds its value unchanged although no new data is present on RDAT 31 0 until the transfer resumes When RVAL is High the RDAT 31 0 RMOD 1 0 RSOP REOP and RERR signals are valid When RVAL is Low the RDAT 3...

Page 46: ...packet data bytes on RDAT 31 0 when REOP is asserted RMOD 1 0 Valid Bytes of RDAT 00 4 bytes 31 0 01 3 bytes 31 8 10 2 bytes 31 16 11 1 byte 31 24 4 x 8 Single PHY mode RMOD 1 0 is not required RMOD is considered valid only when RVAL is simultaneously asserted RENB must be asserted for RMOD 1 0 to be valid RSX NA E13 Output 3 3 V LVTTL Receive Start of Transfer 32 bit Multi PHY mode RSX indicates ...

Page 47: ...tion TX_P_0 TX_P_1 TX_P_2 TX_P_3 Y13 AD13 W16 AC18 Output SerDes Transmit Differential Output Positive TX_N_0 TX_N_1 TX_N_2 TX_N_3 Y14 AD14 Y16 AD18 Output SerDes Transmit Differential Output Negative RX_P_0 RX_P_1 RX_P_2 RX_P_3 P22 V22 T24 U24 Input SerDes Receive Differential Input Positive 1 RX_N_0 RX_N_1 RX_N_2 RX_N_3 R22 U22 R24 V24 Input SerDes Receive Differential Input Negative 1 1 Interna...

Page 48: ...port is configured in copper mode and the RGMII interface is selected only bits TXD 3 0 _n are used The data is transmitted on both edges of TXC_0 3 Fiber Mode The following signals have multiplexed functions when a port is configured in fiber mode TXD4_n TX_DISABLE_0 3 TX_EN_0 TX_EN_1 TX_EN_2 TX_EN_3 AB2 Y8 AC22 V12 Output 2 5 V CMOS Transmit Enable TX_EN indicates that valid data is being driven...

Page 49: ...iber Mode The following signals have multiplexed functions when a port is configured in fiber mode RXD4_n MOD_DEF_0 3 RXD5_n TX_FAULT_0 3 RXD6_n RX_LOS_0 3 RX_DV_0 RX_DV_1 RX_DV_2 RX_DV_3 V5 AB11 Y24 V18 Input 2 5 V CMOS Receive Data Valid RX_DV indicates that valid data is being driven on Receive Data RXD 7 0 _n RX_ER_0 RX_ER_1 RX_ER_2 RX_ER_3 W5 Y12 AA22 U20 Input 2 5 V CMOS Receive Error RX_ER ...

Page 50: ...TD0_3 AA3 Y3 Y2 Y1 AD9 AB9 AB7 AC7 AB23 AB22 AB21 AB20 V17 V16 V15 V14 Output 2 5 V CMOS Transmit Data Bits 3 0 are clocked on the rising edge of TXC Bits 7 4 are clocked on the falling edge of TXC NOTE Shares data signals TXD 3 0 _n with the GMII interface TX_CTL_0 TX_CTL_1 TX_CTL_2 TX_CTL_3 AB2 Y8 AC22 V12 Output 2 5 V CMOS Transmit Control TX_CTL is TX_EN on the rising edge of TXC and a logical...

Page 51: ...ve Control RX_CTL is RX_DV on the rising edge of RXC and a logical derivative of RX_DV and RERR on the falling edge of RXC NOTE RX_CTL shares the same balls as RX_DV on the GMII interface Table 7 CPU Interface Signal Descriptions Sheet 1 of 2 Signal Name Ball Designator Type Standard Description UPX_ADD10 UPX_ADD9 UPX_ADD8 UPX_ADD7 UPX_ADD6 UPX_ADD5 UPX_ADD4 UPX_ADD3 UPX_ADD2 UPX_ADD1 UPX_ADD0 T3 ...

Page 52: ...N5 L4 M3 L3 K3 L2 Input Output 3 3 V LVTTL Data bus 32 bit mode Uses 31 0 16 bit mode Uses 15 0 8 bit mode Uses 7 0 UPX_CS_L R3 Input 3 3 V LVTTL Chip Select Active Low UPX_WR_L T4 Input 3 3 V LVTTL Write Strobe Active Low UPX_RD_L V6 Input 3 3 V LVTTL Read Strobe Active Low UPX_RDY_L M1 Open Drain Output 3 3 V LVTTL Cycle complete indicator Active Low NOTE An external pull up resistor is required...

Page 53: ... GMII Interface NOTE Dual mode I O Normal operation Open drain output Boundary Scan Mode Standard CMOS output MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 MOD_DEF_3 Y6 AD10 W22 T16 Input 2 5 V CMOS MOD_DEF_0 3 inputs determine when an Optical Module Interface is present NOTE These signals are multiplexed with the RXD 4 _n bits of the GMII interface RX_LOS_0 RX_LOS_1 RX_LOS_2 RX_LOS_3 AB5 AA11 V19 T18 Input 2 5 V...

Page 54: ...pen drain output Boundary Scan Mode Standard CMOS output I2 C_CLK L23 Output 2 5 V CMOS I2 C_CLK is the clock used for the I2 C bus interface I2 C DATA_0 I2 C DATA_1 I2 C DATA_2 I2 C DATA_3 L24 M24 N24 P24 Input Open Drain Output 2 5 V CMOS I2 C Data Bus I2 C DATA_0 3 are the data I Os for the I2 C bus interface NOTE An external pull up resistor is required for proper operation NOTE Dual mode I O ...

Page 55: ...ATCH is the latch enable for the LED block Table 12 JTAG Interface Signal Descriptions Signal Name Ball Designator Type Standard Description TCLK J22 Input 3 3 V LVTTL JTAG Test Clock TMS H22 Input 3 3 V LVTTL Test Mode Select TDI J24 Input 3 3 V LVTTL Test Data Input TDO H24 Output 3 3 V LVTTL Test Data Output TRST_L J23 Input 3 3 V LVTTL Test Reset reset input for JTAG test Table 13 System Inter...

Page 56: ...0 AA4 AA17 AC10 AD21 Input Digital ground AVDD1P8_1 A5 A20 Input 1 8 V Analog 1 8 V supply AVDD1P8_2 AB16 T23 Input 1 8 V Analog 1 8 V supply AVDD2P5_1 AD20 Input 2 5 V Analog 2 5 V supply AVDD2P5_2 U14 R18 Input 2 5 V Analog 2 5 V supply VDD A10 D11 F21 J14 K17 L14 P14 R17 U10 AA6 C12 D15 H10 J20 K21 L16 P16 R21 U15 AA10 D6 D19 H15 K4 L9 P9 R4 T11 W4 AA15 D10 F4 J11 K8 L11 P11 R8 T14 W21 AA19 Inp...

Page 57: ...roller 57 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 4 4 Ball Usage Summary Table 15 Ball Usage Summary Type Quantity Inputs 158 Outputs 126 Bi directional 37 Total Signals 321 Power 75 Ground 82 No Connects 74 Total 552 ...

Page 58: ...AC7 AB20 V14 TXD4_0 3 NC TX_DISABLE_0 32 NC AB3 AA7 AD16 AA14 TXD 7 5 _0 TXD 7 5 _1 TXD 7 5 _2 TXD 7 5 _3 NC NC NC Y4 AC9 AA18 W14 AB4 AD8 AA20 AA16 AC3 AB8 AB19 Y15 TX_EN_0 3 TX_CTL_0 3 NC NC AB2 Y8 AC22 V12 TX_ER_0 3 NC NC NC W1 AD6 AD17 AB13 RXC_0 3 RXC_0 3 GND GND V4 AD11 AA24 V23 RXD 3 0 _0 RXD 3 0 _1 RXD 3 0 _2 RXD 3 0 _3 RD 3 0 _0 RD 3 0 _1 RD 3 0 _2 RD 3 0 _3 GND GND Y7 W9 Y23 W18 W7 W11 Y...

Page 59: ...istor is required with most optical modules 2 An open drain I O external 4 7 k Ω pull up resistor is required Table 17 SPI3 MPHY SPHY Interface Sheet 1 of 3 SPI3 Signals Ball Number Comments MPHY SPHY TDAT 31 24 TDAT 7 0 _3 F7 G7 F5 G6 G9 G5 G8 G4 MPHY Consists of a single 32 bit data bus SPHY Separate 8 bit data bus for each Ethernet port TDAT 23 16 TDAT 7 0 _2 C8 E8 F9 E7 E10 E6 E9 E5 TDAT 15 8 ...

Page 60: ...HY and SPHY modes DTPA_0 3 DTPA_0 3 D3 L1 A9 J7 DTPA is available on a per port basis in both MPHY and SPHY modes STPA NC C11 STPA is only applicable in MPHY mode RDAT 31 24 RDAT 7 0 _3 F24 G21 G24 G20 G23 G19 G22 G18 MPHY Consists of a single 32 bit data bus SPHY Separate 8 bit data bus for each Ethernet port RDAT 23 16 RDAT 7 0 _2 E21 C21 E22 C20 D22 B22 C22 B20 RDAT 15 8 RDAT 7 0 _1 F18 E16 E18...

Page 61: ...nal SPHY Each port has a dedicated TSOP_n signal NC RSOP_1 C18 NC RSOP_2 E23 NC RSOP_3 J18 REOP_0 REOP_0 C16 MPHY Use TEOP_0 as the TEOP signal SPHY Each port has a dedicated TEOP_n signal NC REOP_1 D18 NC REOP_2 C23 NC REOP_3 J19 RMOD 1 0 NC G13 G14 RSX and RMOD 1 0 are applicable only in MPHY mode RSX NC E13 Table 18 Definition of Output and Bi directional Balls During Hardware Reset Sheet 1 of ...

Page 62: ...default Bit 4 is driven by the optical module as MOD_DEF_2 TXD 7 0 _3 High Z Fiber mode is the default Bit 4 is driven by the optical module as MOD_DEF_3 TX_EN_0 3 High Z Fiber mode is the default Copper interfaces are disabled TX_ER_0 3 High Z Fiber mode is the default Copper interfaces are disabled RGMII TX_CTL_0 3 High Z Fiber mode is the default Copper interfaces are disabled SerDes TX_P_0 3 0...

Page 63: ...re applied and stable prior to application of the 2 5 V analog and digital supplies 4 7 2 Power Down Sequence Remove the 2 5 V supplies prior to removing the 1 8 V power supplies the reverse of the power up sequence Caution Damage can occur to the ESD structures within the analog I Os if the 2 5 V digital and analog supplies exceed the 1 8 V digital and analog supplies by more than 2 0 V during po...

Page 64: ...y is determined by a number of factors depending on the power management method used NOTE To avoid damage to the IXF1104 MAC the TXAV25 supply must not exceed the VDD supply by more than 2 V at any time during the power up or power down sequence NOTE The 3 3 V supply VDD2 and VDD3 can be applied at any point during this sequence Table 20 Pull Up Pull Down and Unused Ball Guidelines Pin Name Pull U...

Page 65: ...2005 Figure 6 Analog Power Supply Filter Network Table 21 Analog Power Balls Signal Name Ball Designator Comments AVDD1P8_1 A5 A20 Need to provide a filter see Figure 6 R AVDD1P8_1 and AVDD2P5_1 5 6 Ω resistor AVDD2P5_1 AD20 AVDD1P8_2 AB16 T23 Need to provide a filter see Figure 6 R AVDD1P8_2 and AVDD2P5_2 1 0 Ω resistor AVDD2P5_2 U14 R18 ...

Page 66: ... with errors Pre padded RX frames with two bytes aligns the Ethernet payload on SPI3 and in network processor memories Remove CRC from RX frames Append CRC to transmitted frames Performance Monitoring and Diagnostics Loopback modes Detection of runt and overly large packets Cyclic Redundancy Check CRC calculation and error detection RMON statistics for dropped packets packets with errors etc Compl...

Page 67: ... Port_Index 0x18 Note When the user selects the padding function the MAC core adds an automatically calculated CRC to the end of the transmitted packet 5 1 1 2 Automatic CRC Generation Automatic CRC Generation is used in conjunction with the padding feature to generate and append a correct CRC to any transmit frame This feature is enabled by setting bit 6 of the Diverse Config Write Port_Index 0x1...

Page 68: ...Filter VLAN Packets This feature is enabled when bit 3 of the RX Packet Filter Control Port_Index 0x19 1 VLAN frames received in this mode are marked by the MAC to be dropped The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable 0x59F 1 Otherwise the VLAN frame is sent out the SPI3 interface and may optionally be signaled with an RERR see bit 0 in SPI3 Receive Config...

Page 69: ...ting network node to prevent FIFO overruns and dropped packets by managing incoming traffic to fit its available memory The temporary pause allows the device to process packets already received or in transit thus freeing up the FIFO space allocated to those packets Table 22 CRC Errored Packets Drop Enable Behavior CRC Error Pass1 RX FIFO Errored Frame Drop Enable2 RERR Enable3 Actions 1 x x When C...

Page 70: ... Asymmetric Pause Receive direction only Asymmetric Pause Transmit direction only The IXF1104 supports all four options on a per port basis Bits 2 0 of the FC Enable Port_Index 0x12 on page 168 provide programmable control for enabling or disabling flow control in each direction independently The IEEE 802 3x flow control mechanism is accomplished within the MAC sublayer and is based on RX FIFO thr...

Page 71: ... the minimum size 64 bytes Figure 8 and Figure 9 illustrate the frame format and contents Figure 7 Packet Buffering FIFO MDI High Watermark Data Flow MAC Transfer Threshold Low Watermark High Watermark Data Flow Low Watermark RX FIFO High TXPAUSEFR External Strobe 802 3x Pause Frame Generation TX FIFO TX Side MAC RX FIFO 802 3 Flow Control RX Side MAC SPI3 Interface B3231 01 Figure 8 Ethernet Fram...

Page 72: ...hold before the Pause Length time expires the MAC sends another PAUSE frame with the Pause Length time specified as zero This is referred to as XON and informs the link partner to resume normal transmission of packets 5 1 2 1 2 Pause Settings The MAC must send PAUSE frames repeatedly to maintain the link partner in a Pause state The following two inter related variables control this process Pause ...

Page 73: ...low control state the MAC generates a collision for all subsequent receive packets until exiting the flow control state Any receive packet in progress when the MAC enters the flow control state will not be collided with but could be lost due if there is insufficient FIFO depth to complete packet reception Bit 2 of the FC Enable Port_Index 0x12 enables the transmit flow control function 5 1 2 1 5 T...

Page 74: ...Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed in the port 2 FC TX Timer Value Port_Index 0x07 XOFF 0x4 Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed in the port 3 FC TX Timer Value Port_Index 0x07 XOFF 0x5 to 0x6 Reserved Do not use these addresses The TX Pause Control interface will not operate under these conditions 0x7 Transmit...

Page 75: ...isters Port Index Offset on page 156 through Table 69 Optical Module Registers 0x799 0x79F on page 162 are logically split into the following two distinct regions Per Port Registers Global Registers To achieve a desired configuration for a given port the relevant per port registers must be configured correctly by the user The Table 59 through Table 69 also contain registers that affect the operati...

Page 76: ...nable Ports 0 3 0x794 on page 221 to 0x0 prior to any change in the register value This ensures that a change in the MAC clock frequency is controlled correctly If the Clock and Interface Mode Change Enable Ports 0 3 0x794 is not used correctly the IXF1104 MAC may not be configured to the proper mode Port Enable 0x500 0x500 Bit 0 Port 0 Bit 1 Port 1 Bit 2 Port 2 Bit 3 Port 3 Each Port Enable 0x500...

Page 77: ...nization has occurred Both register bits are located in the RX Config Word Port_Index 0x16 If the link goes down after auto negotiation is completed RX_Sync indicates that a loss of synchronization occurred The IXF1104 MAC restarts auto negotiation and attempts to reestablish a link Once a link is reestablished the AN_complete bit is set and the RX_Sync bit shows that synchronization has occurred ...

Page 78: ...ge 163 The IXF1104 MAC duplex setting must be programmed by the system software to match the attached PHY duplex for proper IXF1104 MAC operation 5 1 5 3 Copper Auto Negotiation In the copper MAC auto negotiation and all other controls of the PHY devices are achieved through the MDIO interface and are independent of the MAC controller See Section 5 5 MDIO Control and Interface on page 99 for furth...

Page 79: ...riate counter On reception the MAC transmits these frames across the SPI3 interface jumbo frames above the setting in the RX FIFO Transfer Threshold Port 0 0x5B8 with a bad CRC cannot be dropped and are sent across the SPI3 interface If the receive frame has a bad CRC the appropriate counter is incremented and the RxERR flag is asserted on the SPI3 receive interface Jumbo frames also impact flow c...

Page 80: ...automatically generate Pause control frames to halt the link partner when the High watermark is reached and to restart the link partner when the data stored in the FIFO falls below the low watermark The RX and TX FIFOs have been sized to support lossless flow control with 9 6 KB packets The RX FIFO has a programmable transfer threshold that sets the threshold at which packets become cut through an...

Page 81: ...castPkts Counter32 RxBCPkts TxBCPkts Counter 32 Same as RMON specification etherStatsMulticastPkts Counter32 RxMCPkts TxMCPkts Counter 32 See table note 2 etherStatsCRCAlignErrors Counter32 RxAlignErrors RxFCSErrors TxCRCError Counter 32 The IXF1104 MAC has two counters for the alignment and CRC errors for the RX side only The IXF1104 MAC has a CRC Error counter for the TX side etherStatsUndersize...

Page 82: ... Counter 32 Same a RMON specification etherStatsPkts128to255Octets Counter32 RxPkts128to255Octets TxPkts128to255Octets Counter32 Same a RMON specification etherStatsPkts256to511Octets Counter32 RxPkts256to511Octets TxPkts256to511Octets Counter32 Same a RMON specification etherStatsPkts512to1023Octets Counter32 RxPkts512to1023Octets TxPkts512to1023Octets Counter32 Same a RMON specification etherSta...

Page 83: ... MAC SPI3 Interface is implemented to the System Packet Interface Level 3 SPI3 Physical Layer Interface standard The interface function allows the IXF1104 MAC blocks to interface to higher layer network processors or switch fabric The IXF1104 MAC transmit interface allows data flows from a network processor or switch fabric device to the IXF1104 MAC The receive interface allows data to flow from t...

Page 84: ...ations marked with the TSX signal inactive and the TENB active are packet data for the specified port In the receive direction the IXF1104 MAC specifies the selected port by sending the address on the RDAT 1 0 bus marked with the RSX signal active and RVAL signal inactive All subsequent RDAT 1 0 bus operations marked with RSX inactive and RVAL active are packet data from the specified port Note Se...

Page 85: ...nal word during an active TEOP are indicated by state of TMOD 1 0 5 2 2 2 Receive Timing A packet is received when RSX indicates port address information on the data bus followed by RSOP to indicate the data bus contains the first word of a packet All subsequent data is valid only while RVAL is High and until REOP is asserted Receive data can be temporarily halted when RENB is de asserted and star...

Page 86: ...1 B52 B55 B56 B59 B60 B63 00001 B4 B7 B0 B3 B0660 02 TFCLK TENB TDAT 31 0 TPRTY TERR TSX TSOP TEOP Network Processor SPI3 Bus IXF1104 MPHY Mode Transceiver TFCLK TENB_0 TDAT 31 0 TPRTY_0 TMOD 1 0 TMOD 1 0 RMOD 1 0 RMOD 1 0 TERR_0 TSX TSOP_0 TEOP_0 RFCLK RENB RDAT 31 0 RPRTY RPRTY RVAL RERR RSX RSOP REOP RPRTY_0 RFCLK RENB_0 RDAT 31 0 RVAL_0 RERR_0 RSX RSOP_0 REOP_0 DTPA_0 3 STPA PTPA TADR 1 0 DTPA...

Page 87: ... 5 1 Data Path The IXF1104 MAC SPI3 interface has four 8 bit data paths that can support four independent 8 bit point to point connections in SPHY mode see Figure 16 Since each MAC port has its own dedicated 8 bit SPI3 data bus each port has it own status signal unlike MPHY See the For a detailed list of all the signals refer to the SPI3 pin multiplexing table Furthermore since each port has it ow...

Page 88: ...a on the bus is the first word in the packet All subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted Data transmission can be temporally halted when TENB goes high then resumed when TENB is low 5 2 2 8 Receive Timing SPHY A packet is received when RSOP is asserted to indicate the data bus contains the first word of the packet All subsequent data is valid o...

Page 89: ...4 Port Gigabit Ethernet Media Access Controller 89 Datasheet Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Figure 15 SPHY Receive Logical Timing LK NB OP OP R AT 0 TY AL B0 B2 B1 B62 B63 B0 B1 ...

Page 90: ...g at an overclocked frequency of 125 MHz Note SPHY operates at a maximum frequency of 125 MHz Figure 16 SPHY Connection for Two Intel IXF1104 MAC Ports 8 Bit Interface B0659 02 TFCLK TENB 0 TDAT 7 0 0 TPRTY 0 TERR 0 TSOP 0 TEOP 0 Network Processor SPI3 Bus Intel IXF1104 Port 0 TFCLK TENB_0 TDAT 7 0 _0 TPRTY_0 TERR_0 TSOP_0 TEOP_0 RFCLK RENB 0 RDAT 7 0 0 RPRTY 0 RPRTY_0 RVAL 0 RERR 0 RSOP 0 REOP 0 ...

Page 91: ...s in its receive FIFO it sends the in band address followed by FIFO data to the link layer device in MPHY mode The data on the interface bus is marked with the valid signal RVAL asserted The network processor device can pause the data flow by de asserting the Receive Read Enable RENB signal RENB_0 3 RENB_0 3 controls the flow of data from the IXF1104 MAC RX FIFOs In SPHY mode there is a dedicated ...

Page 92: ... is updated on the rising edge of the TFCLK STPA STPA provides TX FIFO status for the currently selected port in MPHY mode When High STPA indicates that the amount of data in the TX FIFO for the port selected specified by the latest in band address is below the TX FIFO High watermark When the High watermark is crossed STPA transitions Low to indicate the TX FIFO is almost full It stays Low until t...

Page 93: ...onal two bytes This feature was added to the IXF1104 MAC to assist in the design of higher layer memory management The addition of the two extra bytes is not the default operation of the IXF1104 MAC and must be enabled by the user The default operation of the IXF1104 MAC SPI3 receive interface forwards data exactly as it is received by the IXF1104 MAC line interface 5 3 Gigabit Media Independent I...

Page 94: ...ace signal definitions For information on 1000BASE T GMII transmit and receive timing diagrams and tables please refer to Table 49 GMII 1000BASE T Transmit Signal Parameters on page 142 Figure 38 1000BASE T Transmit Interface Timing on page 142 Figure 39 1000BASE T Receive Interface Timing on page 143 and Table 50 GMII 1000BASE T Receive Signal Parameters on page 143 Figure 17 MAC GMII Interconnec...

Page 95: ...t to PHY causes the transmission of error symbols in 1000 Mbps links RXC_0 RXC_1 RXC_2 RXC_3 RX_CLK PHY Receive Clock Continuous reference clock is 125 MHz 100 ppm RXD 7 0 _0 RXD 7 0 _1 RXD 7 0 _2 RXD 7 0 _3 RXD 3 0 PHY Receive Data Bus Width of the bus varies with the speed and mode of operation In 1000 Mbps mode all 8 bits are driven by the PHY device Note MII operation at 10 100 Mbps is not sup...

Page 96: ...te at 125 MHz 100 Mbps operation clocks operate at 25 MHz 10 Mbps operation clocks operate at 2 5 MHz Note The IXF1104 MAC RGMII interface is multiplexed with signals from the GMII interface See Table 16 Line Side Interface Multiplexed Balls on page 58 for detailed information 5 4 1 Multiplexing of Data and Control Multiplexing of data and control information is achieved by utilizing both edges of...

Page 97: ... TXC TX_EN TX_CTL MAC TXEN is on the leading edge of TXC TX_EN xor TX_ER is on the falling edge of TXC RXC_0 3 RXC PHY Continuous reference clock is 125 MHz 25 MHz or 2 5 MHz 50 ppm RD 3 0 _n RD 3 0 PHY Contains register bits 3 0 on the leading edge of RXC and register bits 7 4 on the trailing edge of RXC RX_DV RX_CTL PHY RX_DV is on the leading edge of RXC RX_DV or RXERR is the falling edge of RX...

Page 98: ... 3 0 TD 7 4 TX_EN True TX_ER False TX_EN False TX_ER False TXC_0 3 at Transmitter TD 3 0 _0 3 TX_CTL_0 3 End of Frame TD 3 0 TD 7 4 TX_EN True TX_ER False TX_EN False TX_ER False Valid Frame Frame with Error B3237 01 RXC_0 3 at PHY RD 3 0 _0 3 RX_CTL_0 3 End of Frame RD 3 0 RD 7 4 RX_DV True RX_ER False RX_DV False RX_ER False RXC_0 3 at PHY RD 3 0 _0 3 RX_CTL_0 3 End of Frame RD 3 0 RD 7 4 RX_DV ...

Page 99: ...ps speed although the data may be duplicated on the falling edge of the appropriate clock The MAC holds TX_CTL Low until it is operating at the same speed as the PHY Note The IXF1104 MAC does not support 10 100 Mbps operation when configured in GMII mode 5 5 MDIO Control and Interface The IXF1104 MAC supports the IEEE 802 3 MII Management Interface also known as the Management Data Input Output MD...

Page 100: ...quested single MDIO Read or Write operation This bit is cleared automatically upon operation completion 5 5 4 MDC Generation The MDC clock is used for the MDIO MDC interface The frequency of the MDC clock is selectable by setting bit 0 MDC Speed in an IXF1104 MAC configuration register see Table 145 MDIO Control 0x683 on page 212 5 5 4 1 MDC High Frequency Operation The high frequency MDC is 18 MH...

Page 101: ...me is completed The Write data is first set up in Register 1 bits 15 0 for Write operation Register 0 is initialized with the appropriate control information start op code etc and Register 0 bit 20 is set to logic 1 Register 0 bit 20 is reset to logic 0 when the frame is complete The steps are identical for Read operation except that in Register 1 bits 15 0 the data is ignored The data received fr...

Page 102: ...2 Cnt 2 Cnt 2 Op Code Phy Addr Cnt 2 Cnt 2 Cnt 5 Cnt 5 Reg Addr Cnt 5 Cnt 5 Cnt 5 Cnt 5 Turn Around Cnt 2 Cnt 2 Cnt 2 Data Cnt 16 Cnt 16 Cnt 16 And Go 1 or Cnt 16 and Go 0 MDOE 0 MDO 0 MDC_EN 0 MDOE 1 MDO 1 MDC_EN 1 MDOE 1 MDO Reg_Bit_St Cnt MDC_EN 1 MDOE 1 MDO Reg_Bit_Op Cnt MDC_EN 0 MDOE 1 MDO Reg_Bit_PA Cnt MDC_EN 1 MDOE 1 MDO Reg_Bit_RA Cnt MDC_EN 1 MDOE Wr_Op MDO Reg_Bit_WO Cnt MDC_EN 1 MDOE ...

Page 103: ...the size of the PCB area required to implement this function reduces total power reduces silicon and manufacturing costs and improves reliability Each SerDes interface is identical and fully compliant with the relevant IEEE 802 3 Specifications including auto negotiation Each port is also compliant with and supports the requirements of the Small Form Factor Pluggable SFP Multi Source Agreement MSA...

Page 104: ...ese ten bits have been serialized and transmitted the next word of 10 bit data from the MAC is ready to be serialized for transmission The data is transmitted by the high speed current mode differential SerDes output stage using an internal 1 25 GHz clock generated from the 125 MHz clock input 5 6 2 2 Transmitter Programmable Driver Power Levels The IXF1104 MAC SerDes core has programmable transmi...

Page 105: ...hile a feed forward section suppresses high frequency jitter having limited amplitude The static edge position is held at a constant position in the over sampled by a constant adjustment of the sampling phases with the early and late signals 5 6 2 4 Selective Power Down The IXF1104 MAC offers the ability to selectively power down any of the SerDes TX or RX ports that are not being used This is don...

Page 106: ...al noise component is random and statistical in nature the SerDes core total transmit jitter must be specified as a function of BER 5 6 2 7 Receive Jitter The SerDes core total receiver jitter including contributions from the intermediate frequency PLL is comprised of the following two components A deterministic component attributed to the SerDes core architectural characteristics A random compone...

Page 107: ...each Optical Module Interface that supports a particular media requirement or interface configuration These requirements are detailed in the relevant specifications or manufacturers datasheets IXF1104 MAC 5 7 1 Intel IXF1104 MAC Supported Optical Module Interface Signals To describe the Optical Module Interface operation three supported signal subgroups are required allowing a more explicit defini...

Page 108: ...ct inputs to the IXF1104 MAC and are pulled to a logic Low level during normal operation indicating that a module is present for each channel respectively If a module is not present a logic High is received which is achieved by an external pull up resistor at the IXF1104 MAC device pad The status of each bit one for each port is found in bits 3 0 of the Optical Module Status Ports 0 3 0x799 on pag...

Page 109: ...hese signals are driven to a logic Low level by the IXF1104 MAC during normal operation This indicates that the optical module transmitter is enabled If the optical module transmitter is disabled this signal is switched to a logic High level On the IXF1104 MAC these outputs are open drain types and pulled up by the 4 7 k to 10 k pull up resistor at the Optical Module Interface Each of these signal...

Page 110: ...f byte wide data to the SFP The specific interface in the IXF1104 MAC supports only a subset of the full I C interface and only the features required to support the Optical Module Interfaces are implemented This leads to the following support features Single I2 C_CLK pin connected to all optical modules and implemented to save unnecessary signals use Four per port I2 C_DATA signals I C Data 3 0 ar...

Page 111: ...order of the contiguous accesses required to read the High and Low bytes of 16 bit wide PHY registers Note Only one optical module I C access sequence can be run at any given time If a second write is carried out to the I2 C Control Ports 0 3 0x79B and I2 C Data Ports 0 3 0x79F before a result is returned for the previous write the data for the first write is lost An internal state machine complet...

Page 112: ...hine uses the data from the Write_Data field bits 23 16 of the I2 C Data Ports 0 3 0x79F on page 223 and sets the Write_Complete Register bit 22 of the I2 C Control Ports 0 3 0x79B to 0x1 to signify that the Write Access is complete 6 The data is written through the CPU interface The CPU must poll the Write_Complete bit until it is set to 0x1 It is safe to request a new access only when this bit i...

Page 113: ...CLK High periods indicate a start or stop condition 5 7 3 6 1 Start Condition A High to Low transition of I2 C_DATA with I2 C_CLK High is a start condition that must precede any other command see Figure 26 5 7 3 6 2 Stop Condition A Low to High transition of the I2 C_DATA with I2 C_CLK High is a stop condition After a Read sequence the stop command places the E PROM and the optical module in a sta...

Page 114: ...most significant bits This is common to all devices The next three bits are the A2 A1 and A0 device address bits that are tied to zero in an optical module The eighth bit of the device address is the Read Write operation select bit A Read operation is initiated if this bit is High and a Write operation is initiated if this bit is Low Upon comparison of the device address the optical module outputs...

Page 115: ... and controls the operation of all ports see Table 109 LED Control 0x509 on page 190 Mode 0 LED_SEL_MODE 0 Default This mode selects operations compatible with the SGS Thompson M5450 LED Display Driver device This device converts the serial data stream output by the IXF1104 MAC into 30 direct drive LED outputs Although the LED interface is capable of driving all 30 LEDs only twelve will be driven ...

Page 116: ... is valid during the rising edge of the LED_CLK which clocks the data into the M5450 device The actual data shown in Figure 29 consists of a chain of 36 bits 12 of which are valid LED DATA The 36 bit data chain is built up as follows Table 31 LED Interface Signal Descriptions Pin Name Pin Pin Description LED_CLK K24 This signal is an output that provides a continuous clock synchronous to the seria...

Page 117: ...r chain into the output latches of the 74HC599 device Figure 30 shows that the LED_LATCH signal is active High during the Low period on the 35th LED_CLK cycle This avoids any possibility of trying to latch data as it is shifting through the register When this operation mode is implemented on a board with a shift register chain containing three 74HC599 devices the LED DATA bit 1 is output on Shift ...

Page 118: ... the data decode of the data for both fiber and copper MACs Figure 30 Mode 1 Timing Table 33 Mode 1 Clock Cycle to Data Bit Relationship LED_CLK Cycle LED_DATA Name LED_DATA Description 1 START BIT This bit has no meaning in Mode 1 operation and is shifted out of the 16 stage shift register chain before the LED_LATCH signal is asserted 2 3 PAD BITS These bits have no meaning in Mode 1 operation an...

Page 119: ...Rx LED Green Link LED Green 12 TX LED Green Activity LED Green Table 35 LED Behavior Fiber Mode Type Status Description RXLED Off Synchronization occurs but no packets are received and the Link LED Enable 0x502 is not set Amber On RX Synchronization has not occurred or no optical signal exists Amber Blinking The port has remote fault and the Link LED Enable 0x502 is not set based on remote fault b...

Page 120: ...s in 8 bit mode the data of bytes 0 1 2 is similarly captured in internal write holding registers and the complete 32 bit write is committed when byte 3 is written to the IXF1104 MAC When writing in 16 bit mode bytes 1 0 are captured and the double word is committed when bytes 3 2 are written The complete address for write is ignored except for the write which causes the commit operation Table 36 ...

Page 121: ...d length of time Figure 31 shows the timing of the asynchronous interface for Read access 5 9 1 2 Write Access Write process involves the following Detect assertion of asynchronous Write control signal and latch address Detect de assertion of asynchronous Write control signal and latch data Generate internal Write strobe Assert asynchronous Ready signal for required length of time Figure 32 shows ...

Page 122: ...the Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller The Endian selection is determined by setting the Endian bit in the CPU Interface 0x508 The following describes Endianness control There is a byte swapper between the internal 32 bit bus and the external 32 bit bus In 8 bit or 16 bit mode operation the byte packer byte unpacker holding registers sink and source data just like the 32...

Page 123: ...ate Machine on page 123 and returned to a logic High 5 10 1 TAP State Machine The TAP signals drive a TAP controller which implements the 16 state state machine specified by the IEEE 1149 1 specification Following power up the TAP controller must be reset by one of following two mechanisms Asynchronous reset Synchronous reset Asynchronous reset is achieved by pulsing or holding TRST_L Low Synchron...

Page 124: ...fault instruction is IDCODE The decode logic in the TAP controller selects the appropriate data register and configures the boundary scan cells for the current instruction Table 38 shows the supported boundary scan instructions Table 38 Instruction Register Description Instruction Code Description Data Register BYPASS 1111 1 bit Bypass Bypass EXTEST 0000 External Test Boundary Scan SAMPLE 0001 Sam...

Page 125: ... line side loopback allows the line side receive interface to be looped back to the transmit line side interface A SPI3 loopback mode allows the SPI3 transmit interface to be looped back to the SPI3 receive interface The IXF1104 MAC line side and SPI3 loopback modes are effective diagnostic tools for validation of system level connectivity and interface compatibility In loopback mode operation the...

Page 126: ...s 0 3 0x5B2 must be configured Each IXF1104 MAC port has a unique bit in this register designated to control loopback It is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode 5 11 2 Line Side Interface Loopback To provide a diagnostic loopback feature on the line side interfaces the IXF1104 MAC can be configured to loop back any data receive...

Page 127: ...opback It is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode Note Line side interface loopback packets also appear at the SPI3 interface 5 12 Clocks The IXF1104 MAC system interface has several reference clocks including the following SPI3 data path input clocks RGMII input and output clocks MDIO output clock JTAG input clock I2 C clock L...

Page 128: ... The IXF1104 MAC meets the following specifications for the receive clock 3 3 V LVTTL drive 50 ppm Maximum frequency of 133 MHz in MPHY mode Maximum frequency of 125 MHz in SPHY mode Maximum duty cycle distortion 45 55 5 12 3 RGMII Clocks The RGMII interface is governed by the Hewlett Packard 1 2a specification The IXF1104 MAC compliant to this specification with the following 2 5 V CMOS drive Max...

Page 129: ...drive Maximum clock frequency 11 MHz Maximum duty cycle distortion 40 60 5 12 6 I2 C Clock The IXF1104 MAC supports a single output I2 C clock to support all ten Optical Module interfaces The IXF1104 MAC meets the following specifications for this clock 2 5 V CMOS drive Maximum clock frequency of 100 KHz 5 12 7 LED Clock The IXF1104 MAC supports a serial LED data stream and meets the following spe...

Page 130: ...t Enable 0x500 4 Wait 1 μs 5 De assert set to 0 Clock and Interface Mode Change Enable Ports 0 3 0x794 for the ports being changed 6 Set the speed mode and duplex as follows for the ports being changed a Copper mode Select copper mode for the Interface Mode 0x501 ports Set the per port MAC IF Mode and RGMII Speed Port_Index 0x10 to the appropriate speed and RGMII GMII interface setting Set the per...

Page 131: ...tely reset and flushed to remove packet fragments that may interfere with the auto negotiation process on link recovery 6 2 1 Disable Port Sequence Use the following sequence to disable an individual port 1 Disable the port using MAC port enable disable bits Port Enable 0x500 Bits 3 0 2 Apply TX FIFO soft reset TX FIFO Port Reset 0x620 Bits 3 0 3 Introduce some delay to allow completion of packet ...

Page 132: ...lues listed in Table 41 DC Specifications on page 134 through Table 58 LED Interface AC Timing Parameters on page 154 apply over the recommended operating conditions specified in Table 40 Table 39 Absolute Maximum Ratings Parameter Symbol Min Max Units Comments Supply voltage VDD 0 3 2 2 volts Core digital power VDD2 VDD3 0 3 4 25 volts I O digital power VDD4 VDD5 0 3 4 25 volts I O digital power ...

Page 133: ...5_2 2 3 2 7 Volts Operating Current SerDes Operation Transmitting and receiving in 1000 Mbps mode VDD AVDD1P8_1 AVDD1P8_2 0 780 Amps VDD4 VDD5 AVDD2P5_1 AVDD2P5_2 0 050 Amps VDD2 VDD3 0 246 Amps Operating Current RGMII Operation Transmitting and receiving in 1000 Mbps mode VDD AVDD1P8_1 AVDD1P8_2 0 757 Amps VDD4 VDD5 AVDD2P5_1 AVDD2P5_2 0 224 Amps VDD2 VDD3 0 208 0 235 Amps Recommended operating t...

Page 134: ...Cells Input High voltage VIH 1 7 V 3 3 V LVTTL I Os Input low voltage VIL 0 7 V 3 3 V LVTTL I Os Output High voltage VOH 2 4 V 3 3 V LVTTL I Os Output low voltage VOL 0 4 V 3 3 V LVTTL I Os Table 42 SerDes Transmit Characteristics Sheet 1 of 2 Parameter Symbol Normalized Power Drive Settings1 Min Typ Max Units Comments Transmit differential signal level TxDfPP 0 50 180 230 325 mVpp diff AVDD1P8_2 ...

Page 135: ...xCMV 900 1275 1650 mV Receiver termination impedance RxZ 40 51 62 5 Ω Signal detect level RxSigDet 50 125 200 mVp pdiff Table 43 SerDes Receive Characteristics Parameter Symbol Normalized Power Drive Settings Min Typ Max Units Comments Receiver differential voltage requirement at center of receive eye RxDiffV 200 mVp p diff Receiver common mode voltage range RxCMV 900 1275 1650 mV Receiver termina...

Page 136: ...5 RGMII Power Symbol Parameter Conditions Min Max Units VOH Output High Voltage IOH 1 0 MA VDD MIN 2 0 VDD 3 V VOL Output Low Voltage IOL 1 0 MA VDD MIN GND 3 0 40 V VIH Input High Voltage VIH VIH_MIN VDD MIN VDD 3 V VIL Input Low Voltage VIL VIL_MAX VDD MIN 70 V IIH Input High Current VDD MAX VIN 2 5V 15 µA IIL Input Low Current VDD MAX VIN 0 4V 15 µA ...

Page 137: ...te 27 Oct 2005 7 2 SPI3 AC Timing Specifications 7 2 1 Receive Interface Timing Figure 35 and Table 46 illustrate and provide SPI3 receive interface timing information Figure 35 SPI3 Receive Interface Timing RFCLK RENB RDAT 31 0 RPRY RMOD RSOP REOP RERR RVAL RSX THrenb TSrenb TPrdat TPrprty TPrmod TPrsop TPreop TPrerr TPrval TPrsx ...

Page 138: ...RERR valid 1 5 3 7 ns TPrval RFCLK High to RVAL valid 1 5 3 7 ns TPrsx RFCLK High to RSX valid 1 5 3 7 ns NOTES Receive I O Timing 1 When a setup time is specified between an input and a clock the setup time is the time in nanoseconds from the 1 4 volt point of the input to the 1 4 volt point of the clock 2 When a hold time is specified between an input and a clock the hold time is the time in nan...

Page 139: ...erface Timing Figure 36 and Table 47 illustrate and provide SPI3 transmit interface timing information Figure 36 SPI3 Transmit Interface Timing TFCLK TENB TDAT 31 0 TPRTY TMOD 1 0 TSOP TEOP TERR TADR TSX THtenb TStenb THtdat TStdat THtprty TStrpty THtmod TStmod THtsop TStsop THteop TSteop THterr TSterr THtadr TStadr THtsx TStsx DTPA TPdtpa STPA TPstpa PTPA TPptpa ...

Page 140: ... 1 8 ns THtmod TMOD hold time to TFCLK 0 5 ns TSterr TERR setup time to TFCLK 1 8 ns THterr TERR hold time to TFCLK 0 5 ns TStsx TSX setup time to TFCLK 1 8 ns THtsx TSX hold time to TFCLK 0 5 ns TStadr TADR setup time to TFCLK 1 8 ns THtadr TADR hold time to TFCLK 0 5 ns TPdtpa TFCLK High to DTPA valid 1 5 3 7 ns TPstpa TFCLK High to STPA valid 1 5 3 7 ns TPptpa TFCLK High to PTPA valid 1 5 3 7 n...

Page 141: ...y_G Duty Cycle for 10 100T3 40 50 60 Tr Tf Rise Fall Time 20 80 75 ns 1 This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1 5 ns is added to the associated clock signal 2 For 10 Mbps and 100 Mbps Tcyc scales to 400 ns 40 ns and 40 ns 4 ns respectively 3 Duty cycle may be stretched shrunk during speed changes or while transitioning to a...

Page 142: ...ace Timing Table 49 GMII 1000BASE T Transmit Signal Parameters Symbol Parameter Min Typ1 Max Unit2 t1 TXD 7 0 TXEN TXER Set up to TXC High 2 5 ns t2 TXD 7 0 TXEN TXER Hold from TXC High 0 5 ns t3 TXEN sampled to CRS asserted 16 BT t4 TXEN sampled to CRS de asserted 16 BT 1 Typical values are at 25o C and are for design aid only not guaranteed and not subject to production testing 2 Bit Time BT is ...

Page 143: ...BASE T Receive Signal Parameters Symbol Parameter Min Typ1 Max Unit2 t1 RXD 7 0 RX_DV RXER Setup to Rx_CLK High 2 0 ns t2 RXD 7 0 RX_DV RXER Hold after Rx_CLK High 0 0 ns 1 Typical values are at 25o C and are for design aid only not guaranteed and not subject to production testing 2 Bit Time BT is the duration of one bit as transferred to from the PHY and is the reciprocal of bit rate BT for 1000B...

Page 144: ...57 Revision Number 009 Revision Date 27 Oct 2005 7 5 SerDes AC Timing Specification Figure 40 SerDes Timing Diagram Table 51 SerDes Timing Parameters Symbol Parameter Min Max Units Tt Transmit eye width 800 pS Rt Receiver eye width 280 pS Tv Transmit amplitude 1000 mV Rv Receiver amplitude 200 mV ...

Page 145: ...mode the MDC clock signal operates at a frequency of 2 5 MHz In high speed mode the MDC clock signal operates at a frequency of 18 MHz See Figure 41 through Figure 44 and Table 52 7 6 1 MDC High Speed Operation Timing 7 6 2 MDC Low Speed Operation Timing Figure 41 MDC High Speed Operation Timing Figure 42 MDC Low Speed Operation Timing 24 ns 3 X 125 MHz clocks 32 ns 4 X 125 MHz clocks MDC 56 ns 17...

Page 146: ...gram Table 52 MDIO Timing Parameters Parameter Symbol Min Typ1 Max Units Test Conditions MDIO Setup before MDC t1 10 ns MDC 17 8 MHz 10 ns MDC 2 5 MHz MDIO Hold after MDC t2 10 ns MDC 17 8 MHz 10 ns MDC 2 5 MHz MDC to MDIO Output delay t3 0 42 ns MDC 17 8 MHz 0 300 ns MDC 2 5 MHz 1 Typical values are at 25 o C and are for design aid only not guaranteed and not subject to production testing t1 MDC ...

Page 147: ...gure 46 Write Cycle Diagram Table 53 I2 C AC Timing Characteristics Sheet 1 of 2 Symbol Parameter Min Max Units fSCL Clock frequency SCL 100 kHz tLOW Clock pulse width low 4 7 µs tHIGH Clock pulse width High 4 0 µs tI Noise suppression 100 µs tAA Clock low to data valid out 0 1 4 5 µs tBUF Time the bus must be free before a new transmission starts 4 7 µs tHD STA Start hold time 4 0 µs I2C_Clk I2C_...

Page 148: ...27 Oct 2005 tSU STA Start setup time 4 7 µs tHD DAT Data in hold time 0 µs tSU DAT Data in setup time 200 ns tR Inputs rise time 1 0 µs tF Inputs fall time 300 ns tSU STO Stop setup time 4 7 µs tDH Data out hold time 100 ns tWR Write cycle time 10 ms Table 53 I2 C AC Timing Characteristics Sheet 2 of 2 Symbol Parameter Min Max Units ...

Page 149: ...ming Figure 47 Figure 48 and Table 54 illustrate the CPU interface read and write cycle AC timing 7 8 2 CPU Interface Write Cycle AC Timing Figure 47 CPU Interface Read Cycle AC Timing Figure 48 CPU Interface Write Cycle AC Timing TCAS TCAH TCRR TCDRS TCDRH TCDRD TCRH uPx_ADD 12 0 uPx_RdN uPx_CsN uPx_Data 31 0 uPx_RdyN TCAS TCAH TCWL TCDWS TCDWD TCYD TCWH uPx_Add 12 0 uPx_WrN uPx_CsN uPx_Data 31 0...

Page 150: ... ns Tcrr Ready assertion to read de assertion 10 ns Tcrh Read High width 24 ns Tcdrs Read data setup time to ready assertion 10 ns Tcdrh Read data hold time after read de assertion 8 ns 32 ns Tcdrd Read data driving delay 24 ns 355 ns Tcwl Write assertion width 40 ns Tcwh Ready assertion to write assertion 16 ns Tcdws Write data setup to write de assertion 10 ns Tcdwh Write data hold time after re...

Page 151: ... CLK125 There is however a relationship between the TXPAUSEADD bus and the strobe signal TXPAUSEFR Figure 49 Pause Control Interface Timing Table 55 Transmit Pause Control Interface Timing Parameters Symbol Parameter Min Max Units Tsu TXPAUSEADD stable prior to TXPAUSEFR High 16 ns Tpw TXPAUSEFR pulse width 16 ns Thold TXPAUSEADD stable after TXPAUSEFR High 16 ns TxPauseAdd 1 0 TxPauseFr Tsu min 1...

Page 152: ...ion Figure 50 and Table 56 provide the JTAG AC timing specifications Figure 50 JTAG AC Timing Table 56 JTAG AC Timing Parameters Symbol Parameter Min Max Units Tjc TCLK cycle time 90 ns Tjh TCLK High time 0 4 x Tjc 0 6 x Tjc ns Tjl TCLK low time 0 4 x Tjc 0 6 x Tjc ns Tjval TCLK falling edge to TDO valid 25 ns Tjsu TMS TDI setup to TCLK 20 ns Tjsh TMS TDI hold from TCLK 5 ns ...

Page 153: ...ber 009 Revision Date 27 Oct 2005 7 11 System AC Timing Specification Figure 51 and Table 57 illustrate the system reset AC timing specifications Figure 51 System Reset AC Timing Table 57 System Reset AC Timing Parameters Symbol Parameter Min Max Units Trw Reset pulse width 1 0 µs Trt Reset recovery time 200 µs ...

Page 154: ...gure 52 LED AC Interface Timing Table 58 LED Interface AC Timing Parameters Symbol Parameter Min Max Units Tcyc LED_CLK cycle time 1 36 1 40 ms Thi LED_CLK High time 680 700 µs Tlow LED_CLK low time 680 700 µs Tdatd LED_CLK falling edge to LED_DATA valid 2 5 ns Tlath LED_CLK rising edge to LED_LATCH rising edge 690 700 µs Tlatl LED_CLK falling edge to LED_LATCH falling edge 690 700 µs LED_CLK LED_...

Page 155: ...ed descriptions of each register segment or bit All registers are accessed and addressed as 32 bit doublewords When accessed using 8 or 16 bit accesses the CPU interface packs or unpacks the partial accesses into a 32 bit register value 8 2 Graphical Representation Figure 53 represents an overview of the IXF1104 MAC global control status registers that are used to configure or report on all ports ...

Page 156: ... a per port basis Note All IXF1104 MAC registers are 32 bits Figure 54 Register Overview Diagram Port Select Global Registers Per Port Registers 10 0 6 Table 59 MAC Control Registers Port Index Offset Sheet 1 of 2 Register Bit Size Mode1 Ref Page Offset Station Address Port_Index 0x00 0x01 Low 32 R W 163 0x00 Station Address Port_Index 0x00 0x01 High 32 R W 163 0x01 Desired Duplex Port_Index 0x02 ...

Page 157: ...dress Port_Index 0x1A 0x1B PortMulticastAddressLow 32 R W 173 0x1A Port Multicast Address Port_Index 0x1A 0x1B PortMulticastAddressHigh 32 R W 173 0x1B Table 60 MAC RX Statistics Registers Port Index Offset Sheet 1 of 2 Register Bit Size Mode1 Ref Page Offset RxOctetsTotalOK 32 R 174 0x20 RxOctetsBAD 32 R 174 0x21 RxUCPckts 32 R 174 0x22 RxMCPkts 32 R 174 0x23 RxBCPkts 32 R 174 0x24 RxPkts64Octets...

Page 158: ...BCPkts 32 R 178 0x44 TxPkts64Octets 32 R 178 0x45 TxPkts65to127Octets 32 R 178 0x46 TxPkts128to255Octets 32 R 178 0x47 TxPkts256to511Octets 32 R 178 0x48 TxPkts512to1023Octets 32 R 178 0x49 TxPkts1024to1518Octets 32 R 178 0x4A TxPkts1519toMaxOctets 32 R 178 0x4B TxDeferred 32 R 178 0x4C TxTotalCollisions 32 R 178 0x4D TxSingleCollisions 32 R 178 0x4E TxMultipleCollisions 32 R 178 0x4F TxLateCollis...

Page 159: ...ters 0x500 0X50C Register Bit Size Mode1 Ref Page Address Port Enable 0x500 32 R W 188 0x500 Interface Mode 0x501 32 R W 188 0x501 Link LED Enable 0x502 32 R W 189 0x502 Reserved 32 RO 0x503 0x504 MAC Soft Reset 0x505 32 R W 189 0x505 MDIO Soft Reset 0x506 32 R W 190 0x506 Reserved 32 RO 0x507 CPU Interface 0x508 32 R W 190 0x508 LED Control 0x509 32 R W 190 0x509 LED Flash Rate 0x50A 32 R W 191 0...

Page 160: ...p Counter Port 3 32 R 198 0x5A5 Reserved 32 RO 0x5A6 0x5B1 RX FIFO SPI3 Loopback Enable for Ports 0 3 0x5B2 32 R W 199 0x5B2 RX FIFO Padding and CRC Strip Enable 0x5B3 32 R W 200 0x5B3 Reserved 32 R 0x5B4 0x5B7 RX FIFO Transfer Threshold Port 0 0x5B8 32 R W 201 0x5B8 RX FIFO Transfer Threshold Port 1 0x5B9 32 R W 201 0x5B9 RX FIFO Transfer Threshold Port 2 0x5BA 32 R W 201 0x5BA RX FIFO Transfer T...

Page 161: ...R 209 0x625 TX FIFO Errored Frame Drop Counter Port 1 32 R 209 0x626 TX FIFO Errored Frame Drop Counter Port 2 32 R 209 0x627 TX FIFO Errored Frame Drop Counter Port 3 32 R 209 0x628 Reserved 32 R 0x629 0x62C TX FIFO Occupancy Counter for Port 0 32 R 210 0x62D TX FIFO Occupancy Counter for Port 1 32 R 210 0x62E TX FIFO Occupancy Counter for Port 2 32 R 210 0x62F TX FIFO Occupancy Counter for Port ...

Page 162: ...x785 0x786 TX and RX Power Down 0x787 32 R W 220 0x787 Reserved 32 RO 0x788 0x792 RX Signal Detect Level Ports 0 3 0x793 32 R W 220 0x793 Clock and Interface Mode Change Enable Ports 0 3 0x794 32 R W 221 0x794 Reserved 32 RO 0x795 0x798 Table 69 Optical Module Registers 0x799 0x79F Register Bit Size Mode1 Ref Page Address Optical Module Status Ports 0 3 0x799 32 R 222 0x799 Optical Module Control ...

Page 163: ...eiving side Bits 15 0 of this register are assigned to bits 47 32 of the station address Port_Index 0x01 R W 0x00000000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 71 Desired Duplex Port_Index 0x02 Bit Name Description Type1 Default Register Description Chooses between half duplex and full duplex operation in RGMII...

Page 164: ...Only valid in half duplex Port_Index 0x06 R W 0x0000000F 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 75 FC TX Timer Value Port_Index 0x07 Name Description Address Type1 Default FC TX Timer Value The 16 bit pause length inserted in the flow control pause frame sent to the receiving station The value is in 512 bit ti...

Page 165: ...is is only used in half duplex operation It starts counting at the same time as RXIPG1 Once RXIPG1 expires a frame is transmitted when RXIPG2 expires regardless of the CRS value If CRS is asserted before RXIPG1 expires no transmission occurs and both RXIPG1 an RXIPG2 are reset once CRS is de asserted again The value specified in this register is calculated as follows register_value 5 8 RXIPG2 in t...

Page 166: ...nk partner is kept in pause mode continuously Port_Index 0x0E R W 0x0000002F 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 81 Max Frame Size Addr Port_Index 0x0F Name Description Address Type1 Default Max Frame Size This is a 14 bit value configuring the maximum frame size the MAC can receive or transmit without acti...

Page 167: ...e and speed 0x00000003 31 3 Reserved Reserved R 0x00000000 2 0 Port Mode These bits are used to define the clock mode and the RGMII GMII mode of operation 000 Reserved 001 Reserved 010 GMII 1000 Mbps operation 011 Reserved 100 RGMII 10 Mbps operation 101 RGMII 100 Mbps operation 11x RGMII 1000 Mbps operation R W 011 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write N...

Page 168: ...able watermarks or the Transmit Pause Control interface R W 1 0 RX FDFC 0 Disable RX full duplex flow control the MAC will not respond to flow control frames sent to it by the link partner 1 Enable RX full duplex flow control MAC will respond to flow control frames sent by the link partner and will stop packet transmission for the time specified in the flow control frame R W 1 1 RO Read Only No cl...

Page 169: ...Default Register Description Discards or forwards unknown control frames Known control frames are pause frames 0x00000000 31 1 Reserved Reserved R 0x00000000 0 Discard Unknown Control Frame 0 Forward unknown control frames 1 Discard unknown control frames R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 88 RX Conf...

Page 170: ...e ability to send pause frames RO 0 7 Sym Pause Sym Pause The ability to send and receive pause frames RO 0 6 Half Duplex Half duplex RO 0 5 Full Duplex Full duplex RO 0 4 0 Reserved Reserved RO 0x0 Table 89 TX Config Word Port_Index 0x17 Sheet 1 of 2 Bit Name Description Type1 Default Register Description This register is used in fiber MAC for auto negotiation only The contents of this register a...

Page 171: ...ead R W 0x0 8 Reserved2 Write as 1 ignore on Read R W 1 7 pad_enable 0 Normal operation 1 Enable padding of undersized packets NOTE Assertion of this bit results in the automatic addition of a CRC to the padded packet R W 0 6 crc_add 0 Normal operation 1 Enable automatic CRC appending R W 0 5 AN_enable Enable auto negotiation used for fiber mode only to be performed by the hardware state machines ...

Page 172: ...ad 2 1 Frames with a CRC Error are not marked as bad and are passed to the SPI3 interface for transfer as good frames regardless of the state of the bits in the RX FIFO Errored Frame Drop Enable 0x59F NOTE When the CRC Error Pass Filter bit 0 it takes precedence over the other filter bits Any packet whether is a Pause Unicast Multicast or Broadcast packet with a CRC error is marked as a bad frame ...

Page 173: ... on the unicast address R W 0 Table 92 Port Multicast Address Port_Index 0x1A 0x1B Name Description Address Type Default Port Multicast Address Low This address compares against multicast frames at the receiving side if multicast filtering is enabled This register contains bits 31 0 of the address Port_Index 0x1A R W 0x0000000 Port Multicast Address High This address compares against multicast fra...

Page 174: ... packets which are also counted in other counters These packet types are counted twice Take care when summing register counts for reporting Management Information Base MIB information Port_Index 0x22 R 0x00000000 RxMCPkts The total number of multicast packets received excluding bad packets Note This count includes pause control packets which are also counted in the PauseMacControl ReceivedCounter ...

Page 175: ...han 1518 octets in length Incremented for tagged packet with a length between 1523 max frame size including the tag Port_Index 0x2B R 0x00000000 RxFCSErrors Number of frames received with legal size but with wrong CRC field also called Frame Check Sequence FCS field NOTE Legal size is 64 bytes through the value programmed in the Max Frame Size Addr Port_Index 0x0F on page 166 Port_Index 0x2C R 0x0...

Page 176: ...31 R 0x00000000 RxPauseMacContr olReceivedCounter Number of Pause MAC control frames received This statistic register increments on any valid 64 byte pause frame with a valid CRC and also increments on a 64 byte pause frame with an invalid CRC if bit 5 of the RX Packet Filter Control Port_Index 0x19 is set to 1 Port_Index 0x32 R 0x00000000 RxUnknownMac ControlFrame Counter Number of MAC control fr...

Page 177: ...nly fully updated after reception of a good frame following a fragment NOTE This register is only relevant when the IXF1104 MAC port is configured for copper operation the line side interface is configured for either RGMII or GMII operation This register will not increment when the IXF1104 MAC port is configured for fiber operation using the SerDes interface Port_Index 0x36 R 0x00000000 RxCarrier ...

Page 178: ...count includes all bytes from the destination MAC address to and including the CRC The initial preamble and SFD bytes are not counted Late collision counted The count is close to the actual number of bytes transmitted before the frame is discarded Excessive collision counted The count is close to the actual number of bytes transmitted before the frame is discarded TX under run counted The count is...

Page 179: ...ncluding tag field Port_Index 0x48 R 0x00000000 Txpkts512to1023Octets The total number of packets transmitted including bad packets that were 512 1023 octets in length Incremented for tagged packets with a length of 512 1023 bytes including tag field Port_Index 0x49 R 0x00000000 Txpkts1024to1518Octets The total number of packets transmitted including bad packets that were 1024 1518 octets in lengt...

Page 180: ...r than 512 bit times into the transmission of a packet Such frame are terminated and discarded NOTE NA half duplex only Port_Index 0x50 R 0x00000000 TxExcessiveCollisionErrors A count of frames which collides 16 times and is then discarded by the MAC Not effecting xMultipleCollisions NOTE NA half duplex only Port_Index 0x51 R 0x00000000 TxExcessiveDeferralErrors Number of times frame transmission ...

Page 181: ...tional frames The port must be in half duplex mode with flow control enabled NOTE To receive a correct statistic a last frame may have to be transmitted after the last flow control collisions send NOTE NA half duplex only Port_Index 0x58 R 0x00000000 Table 95 PHY Control Port Index 0x60 Sheet 1 of 2 Bit Name Description Type1 Default 0x00000010 001000 31 16 Reserved Reserved RO 0x0000 15 Reset PHY...

Page 182: ...1000 Mbps manual mode now allowed 11 Reserved RO 02 5 0 Reserved Reserved RO 0 Table 96 PHY Status Port Index 0x61 Sheet 1 of 2 Bit Name Description Type1 Default 0x001111001 00001001 31 16 Reserved Reserved RO 0 15 100BASE T4 0 PHY not able to operate in 100BASE T4 1 PHY able to operate in 100BASE T4 RO 0 14 100BASE X Full Duplex 0 PHY not able to operate in 100BASE X in full duplex mode 1 PHY ab...

Page 183: ...ion 0 PHY will not accept management frames with preamble suppressed 1 PHY will accept management frames with preamble suppressed RO 0 5 Reserved Reserved RO 0 4 Remote Fault 0 1 Remote fault condition detected RO 0 3 Auto Negotiation Ability 0 1 PHY is able to perform auto negotiation RO 1 2 Link Status 0 Link is down 1 Link is up RO 0 1 Jabber Detect 0 Jabber condition not detected 1 Jabber cond...

Page 184: ...4 Reserved Reserved RO 0 13 Remote Fault 0 No remote fault 1 Remote fault RO 0 12 Reserved Reserved RO 0 11 ASM_DIR Advertise Asymmetric Pause Direction register bit This register bit is used in conjunction with Pause Register bit 4 10 0 Link partner is not capable of asymmetric pause 1 Link partner is capable of asymmetric pause RO 1 10 Pause Advertise to link partner that Pause operation is desi...

Page 185: ...01001111000 01 31 16 Reserved Reserved RO 0 15 Next Page 0 Link partner has no ability to send multiple pages 1 Link partner has the ability to send multiple pages RO NA 14 Acknowledge 0 Link partner has not received Link Code Word from the IXF1104 MAC 1 Link partner has received Link Code Word from the IXF1104 MAC RO NA 13 Remote Fault 0 No remote fault 1 Remote fault RO NA 12 Reserved Reserved R...

Page 186: ...nspecified or reserved combinations should not be transmitted Setting this field to a value other than 00001 will most likely cause auto negotiation to fail RO 00001 Table 101 Auto Negotiation Expansion Port Index 0x66 Sheet 1 of 2 Bit Name Description Type1 Default 0x0000000 31 6 Reserved Reserved RO 0 5 Base Page This register bit indicates the status of the auto negotiation variable base page I...

Page 187: ...egotiation Next Page Transmit Port Index 0x67 Bit Name Description Type1 Default 0x0000000 31 16 Reserved Reserved RO 0 15 Next Page NP 0 Last page 1 Additional Next Pages follow RO 0 14 Reserved Reserved RO 0 13 Message Page MP 0 Unformatted page 1 Message page RO 0 12 Acknowledge 2 0 Cannot comply with message 1 Complies with message RO 0 11 Toggle T 0 Previous value of the transmitted Link Code...

Page 188: ...ort 0 0 Disable 1 Enable R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 104 Interface Mode 0x501 Bit Name Description Type1 Default Register Description If_Mode Four bits of this register determines the PHY interface mode 0 Fiber SerDes OMI interface 1 Copper GMII or RGMII interface Changes to the data setting o...

Page 189: ...ink R W 0 0 Link LED Enable Port 0 Port 0 link 0 No link 1 Link R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 106 MAC Soft Reset 0x505 Bit Name Description Type1 Default Register Description Per port software activated reset of the MAC core 0x00000000 31 4 Reserved Reserved R W 0x00000 3 Software Reset MAC 3 Po...

Page 190: ...RO 0x00 24 CPU Endian Reserved in Little Endian Valid in Big endian 0 Little Endian 1 Big Endian R W 0 23 1 Reserved Reserved RO 0x000000 0 CPU Endian Control Reserved in Big Endian Valid in Little Endian 0 Little Endian 1 Big Endian R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write NOTE Since the Endianess of the bus is...

Page 191: ...on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 111 LED Fault Disable 0x50B Bit Name Description Type1 Default Register Description Per port fault disable Disables the LED flashing for local or remote faults 0x00000000 31 4 Reserved Reserved RO 0x0000000 3 LED Port 3 Fault Control Port 3 0 Fault enabled 1 Fault disabled R W 0 2 LED Port 2 Fau...

Page 192: ...icon stepping The next 16 bits store a Part ID Number The next 11 bits contain a JEDEC manufacturer ID Bit zero 1 if the chip is the first in a stack The encoding scheme used for the Product ID field is implementation dependent 0x10450013 31 28 Version Version RO 00012 27 12 Part ID Part ID RO 0000010001 010000 11 8 JEDEC Continuation Characters JEDEC Continuation Characters RO 0000 7 1 JEDEC ID J...

Page 193: ...alue of 0x0E6 represents 230 eight byte locations This equates to 1840 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data stored in the RX FIFO exceeds the high watermark flow control is automatically initiated within the MAC to avoid an overflow condition 0x0E6 31 12 Reserved Reserved RO 0x00000 11 0 RX FIFO High Watermark Port 1 The high water mark val...

Page 194: ... unit entry in this register equates to 8 bytes of data When the amount of data stored in the RX FIFO falls below the Low Watermark flow control is automatically de asserted within the MAC to allow more line side data to be captured by the RX FIFO 0x072 31 12 Reserved Reserved RO 0x00000 11 0 RX FIFO Low Watermark Port 0 The High Watermark value NOTE Should never be greater or equal to the High Wa...

Page 195: ...elow the Low watermark flow control is automatically de asserted within the MAC to allow more line side data to be captured by the RX FIFO 0x072 31 12 Reserved Reserved RO 0x00000 11 0 RX FIFO Low Watermark Port 3 The High watermark value NOTE Should never be greater or equal to the High Watermark R W 0x072 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R...

Page 196: ...Reset RX FIFO for Port 1 Port 1 0 De assert reset 1 Reset R W 0 0 Reset RX FIFO for Port 0 Port 0 0 De assert reset 1 Reset R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 123 RX FIFO Errored Frame Drop Enable 0x59F Sheet 1 of 2 Bit Name Description Type1 Default Register Description This register configures the ...

Page 197: ...A0 Bit Name Description Type1 Default Register Description This register provides a status if a FIFO full situation occurs for example a FIFO overflow The bit position equals the port number This register is cleared on Read 0x00000000 31 4 Reserved Reserved RO 0x0000000 3 RX FIFO Overflow Event on Port 3 Port 3 0 FIFO overflow event did not occur 1 FIFO overflow event occurred R 0 2 RX FIFO Overfl...

Page 198: ...ved in conjunction with the RX FIFO Errored Frame Drop Enable 0x59F and the RX Packet Filter Control Port_Index 0x19 Frames are greater than the Max Frame Size Addr Port_Index 0x0F This register is cleared on Read 0x5A2 R 0x00000000 RX FIFO Errored Frame Drop Counter on Port 1 This register counts all frames dropped from the RX FIFO for port 1 by meeting one of the following conditions Frames are ...

Page 199: ... are greater than the Max Frame Size Addr Port_Index 0x0F This register is cleared on Read 0x5A5 R 0x00000000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 126 RX FIFO SPI3 Loopback Enable for Ports 0 3 0x5B2 Bit Name Description Type1 Default Register Description Enables the TX SPI3 port to send packets into the RX_...

Page 200: ... stripping is enabled for Port 1 0 Disabled 1 Enabled R W 0 4 CRC Stripping Enable for Port 0 CRC stripping is enabled for Port 0 0 Pre pending Disabled 1 Pre pending Enabled R W 0 3 Pre pending Enable2 Port 3 Enables pre pending of two bytes at the start of every packet Port 3 0 Disabled 1 Enabled R W 0 2 Pre pending Enable2 Port 2 Enables pre pending of two bytes at the start of every packet Por...

Page 201: ...hreshold below a setting of 0xBE 1520bytes R W 0x0BE 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 129 RX FIFO Transfer Threshold Port 1 0x5B9 Bit Name Description Type Default Register Description RX FIFO transfer threshold for port 1in 8 byte location 0x000000BE 31 12 Reserved Reserved RO 0x00000 11 0 RX FIFO Trans...

Page 202: ...reshold below a setting of 0xBE 1520bytes R W 0x0BE 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 131 RX FIFO Transfer Threshold Port 3 0x5BB Bit Name Description Type Default Register Description RX FIFO transfer threshold for port 3 in 8 byte location 0x000000BE 31 12 Reserved Reserved RO 0x00000 11 0 RX FIFO Trans...

Page 203: ...the amount of data stored in the TX FIFO exceeds the high watermark flow control is automatically initiated on the SPI3 interface to request that the switch fabric stops data transfers to avoid an overflow condition 0x601 R W 0x000003E0 TX FIFO High Watermark Port 2 High watermark for TX FIFO Port 2 The default value of 0x3E0 represents 992 8 byte locations This equates to 7936 bytes of data A uni...

Page 204: ...rmark flow control is automatically de asserted on the SPI3 interface to allow further data to be sent by the switch fabric to the IXF1104 MAC 0x60B R W 0x000000D0 TX FIFO Low Watermark Port 2 Low watermark for TX FIFO Port 2 The default value of 0x0D0 represents 208 8 byte locations This equates to 1664 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data...

Page 205: ...appropriate value the user can configure the TX FIFO to operate in a cut through mode rather than the default store and forward operation mode 0x615 R W 0x000001BE TX FIFO MAC Threshold Port 2 MAC threshold for TX FIFO Port 2 The default value of 0x1BE represents 446 8 byte locations This equates to 3568 bytes of data A unit entry in this register equates to 8 bytes of data When the amount of data...

Page 206: ...bit position equals the port number This register is cleared on Read 0x0 31 12 Reserved Reserved RO 0x00000 11 FOSE3 Port 3 0 FIFO out of sequence event did not occur 1 FIFO out of sequence event occurred R 0 10 FOSE2 Port 2 0 FIFO out of sequence event did not occur 1 FIFO out of sequence event occurred R 0 9 FOSE1 Port 1 0 FIFO out of sequence event did not occur 1 FIFO out of sequence event occ...

Page 207: ...Port 1 Line Side Loopback 0 Disable line side loopback 1 Enable line side loopback R W 0 0 Port 0 Line Side Loopback 0 Disable line side loopback 1 Enable line side loopback R W 0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 137 TX FIFO Port Reset 0x620 Sheet 1 of 2 Bit Name Description Type1 Default Register Descri...

Page 208: ...rt 1 becomes full or reset the number of frames lost or removed on this port is shown in this register This register is cleared on Read 0x622 R 0x00000000 TX FIFO overflow frame drop counter on Port 2 When TX FIFO on Port 2 becomes full or reset the number of frames lost or removed on this port is shown in this register This register is cleared on Read 0x623 R 0x00000000 TX FIFO overflow frame dro...

Page 209: ...t with no EOP Small Packets 9 14 bytes Frames received that are signaled with TERR on the SPI3 TX interface NOTE This register is cleared on Read 0x626 R 0x00000000 TX FIFO errored frame drop counter on Port 2 This register provides the number of packets dropped by the TX FIFO due to the following Data Parity Errors Short SOPs two consecutive SOPs for a port with no EOP Small Packets 9 14 bytes Fr...

Page 210: ...630 R 0x00000000 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 141 TX FIFO Port Drop Enable 0x63D Bit Name Description Type Default Register Description Independently enables the individual TX FIFOs to drop erroneous packets 0x0000000f 31 4 Reserved Reserved RO 0x000000 3 Port 3 Drop 0 Disable the TXFIFO from droppin...

Page 211: ...rmed 00 Reserved 01 Write operation as defined in IEEE 802 3 clause 22 2 4 5 10 Read operation as defined in IEEE 802 3 clause 22 2 4 5 11 Reserved R W 01 15 10 Reserved Reserved RO 000000 9 8 PHY Address Sets bits 1 0 of the external PHY address Bits 4 2 of the PHY address are fixed at 000 R W 00 7 5 Reserved Reserved RO 000 4 0 REG Address Five bit address to one among 32 registers in an address...

Page 212: ...ead Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 145 MDIO Control 0x683 Bit Name Description Type1 Default Register Description Miscellaneous control bits 0x00000000 31 4 Reserved Reserved RO 0x000 3 MDIO in Progress MDIO progress This bit reflects the status of MDIO transaction 0 MDIO Single command not in progress 1 MDIO Single Command in progress RO 0...

Page 213: ... R W 1 20 Tx_ad_prtyer_drop Indicates whether to drop packets received with parity error during the address selection phase Tsx and nTenb High should be dropped 0 Do not drop packets with address parity error 1 Drop packets with address parity error This is applicable only in MPHY mode of operation This bit is ignored in SPHY 4 x 8 mode as there will be no address selection R W 0 19 Dat_prtyer_drp...

Page 214: ...Parity 1 Even Parity MPHY Mode NA R W 0 5 Tx_parity_sense Port 1 SPHY Mode Indicates the parity sense to check the parity on TDAT bus for port 1 0 Odd Parity 1 Even Parity MPHY Mode NA R W 0 4 Tx_parity_sense Port 0 SPHY Mode Indicates the parity sense to check the parity on TDAT bus for port 0 0 Odd Parity 1 Even Parity MPHY Mode Indicates the parity sense to check the parity on TDAT bus for all ...

Page 215: ...ort 0 R W 1 Table 147 SPI3 Receive Configuration 0x701 Sheet 1 of 4 Bit Name Description Type1 Default Register Description This register gives the configuration related to the SPI3 receiver 0x00000F80 31 28 Reserved Reserved RO 0x0 27 B2B_PAUSE Port 3 SPHY Mode Indicates the number of pause cycles to be introduced between back to back transfers for port 3 0 Zero pause cycles 1 Two pause cycles MP...

Page 216: ...er of pause cycles to be introduced between back to back transfers for all ports 0 Zero pause cycles 1 Two pause cycles R W 0 23 22 RX_BURST Port 3 SPHY Mode NA MPHY Mode NA R W 0x0 21 20 RX_BURST Port 2 SPHY Mode NA MPHY Mode NA R W 0x0 19 18 RX_BURST Port 1 SPHY Mode NA MPHY Mode NA R W 0x0 17 16 RX_BURST Port 0 SPHY Mode NA MPHY Mode Selects the maximum burst size on the RX path for all ports 0...

Page 217: ...Mode Indicates the parity sense to check the parity on RDAT bus for port 0 0 Odd Parity 1 Even Parity MPHY Mode Indicates the parity sense to check the parity on RDAT bus for all ports 0 Odd Parity 1 Even Parity R W 0x0 11 Rx_port_enable Port 3 SPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected SPI3 RX port MPHY Mode 0 Disables the selected SPI3 RX port 1 Enables the selected SP...

Page 218: ... core 1 Enables the RX SPI3 core R W 0x1 6 1 IBA 5 0 SPHY Mode NA Write as 0 ignore on Read MPHY Mode Sets the 6 bit value appended to the 2 bit address during the port address selection R W 0x00 0 RERR_enable SPHY Mode MPHY Mode Frames marked to be filtered based on the settings in the RX Packet Filter Control Port_Index 0x19 or frames above the Max Frame Size Addr Port_Index 0x0F that are not dr...

Page 219: ...on cycle 0x00000000 31 8 Reserved Reserved RO 0x000000 7 0 Address Parity Error Packet Drop Counter This is an 8 bit counter that counts the number of packets dropped due to parity error detection during the address selection cycle This gets cleared when read and saturates at 8 hFF There is only one counter for address parity drop as address will be used only in MPHY mode of operation The counter ...

Page 220: ...oded input that sets Power Level for Port 0 R W 1101 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 150 TX and RX Power Down 0x787 Bit Name Description Type Default Register Description TX and RX power down bits to allow per port power down of unused ports 0x00000000 31 14 Reserved Reserved RO 0x0000000 13 10 TPWRDWN ...

Page 221: ...o sample the MAC IF Mode and RGMII Speed Port_Index 0x10 and the Interface Mode 0x501 0 Set to zero when changes are being made to the MAC IF Mode and RGMII Speed Port_Index 0x10 and the Interface Mode 0x501 1 Set to 1 for the configuration changes to take effect R W 0 1 Clock and Interface Mode Change Enable Port 12 Enables internal clock generator for Port 1 to sample the MAC IF Mode and RGMII S...

Page 222: ...ts for Ports 0 3 R 0x0 9 4 Reserved Reserved 0X00 3 0 MOD_DEF_3 0 MOD_DEF inputs for Ports 0 3 R 0x0 1 RO Read Only No clear on Read R Read Clear on Read W Write only R W Read Write No clear R W C Read Write Clear on Write Table 154 Optical Module Control Ports 0 3 0x79A Bit Name Description Type1 Default Register Description This register provides access to optical module interrupt enables and se...

Page 223: ... Reserved RO 0 17 16 Port Select Selects the port for which the I2 C transaction is targeted Valid range is 0 to 3 R W 00 15 Read Write 0 Write transaction 1 Read transaction R W 0 14 11 Device ID Most significant four bits of device address field R W 0x0 10 0 Register Address Bits 10 8 select the least significant three bits of the device address field Bits 7 0 select the word register address R ...

Page 224: ...rical performance and are recommended for high power applications with high noise immunity requirements Note The FC PBGA package will not be available until mid 2006 Please see your field sales representative for more detailed information 9 1 1 Features Flip chip die attach surface mount second level interconnect High electrical performance High I O counts Area array I O options Multiple power zon...

Page 225: ... Figure 56 illustrate the CBGA top bottom and side package views Figure 55 CBGA Package Diagram B0034 01 3 902 3 938 Chip Substrate 7 804 7 877 25 0 2 25 0 2 47P6802 Note All dimensions are in mm B0035 03 25 0 2 23 25 0 2 23 23x TYP Chip Carrier A01 Corner 23x TYP 0 825 MAX 0 325 MIN Reference 0 825 MAX 0 325 MIN 575X ø 0 8 0 05 I O Pads Reference ø 0 20 D A L S B S Note All dimensions are in mm B...

Page 226: ...ision Date 27 Oct 2005 Figure 56 CBGA Package Side View Diagram B0555 01 Seating Plane 0 15 C 4 237 Max 3 619 Min 3 327 Max 2 809 Min 0 857 Max 0 779 Min 4 16 Max 3 43 Min 6X 3 24 Max 2 72 Min 6X 2 47 Max 2 03 Min 0 81 0 1 0 77 Max 0 69 Min 6X Chip C4 Encapsulant Fillet 45L4867 552 Solder ball Note All dimensions are in mm ...

Page 227: ...ecifications Note Please contact your field sales representative for more information on the FC PBGA package Figure 57 FC PBGA Package Top and Bottom Views B5181 02 Basic 1 00 mm Basic 1 00 mm ł eee 0 25 ł b 0 55 min 0 75 max 01 Terminal A01 Identifier Lid Seating Plane Substrate A B C 02 03 C A M B ł fff 0 10 C M e A E D e No Ball Ball Notes All dimensions are in millimeters Legend TOP VIEW BOTTO...

Page 228: ...Intel IXF1104 4 Port Gigabit Ethernet Media Access Controller Datasheet 228 Document Number 278757 Revision Number 009 Revision Date 27 Oct 2005 Figure 58 FC PBGA Mechanical Specifications ...

Page 229: ...Silicon revision number A0 A1 B0 Note Diameter of Trademark Circles are 70 mils Height of circles surrounding Pb redced symbol are equal to overall character height Substrate PN Substrate material number barely visible JJJJJJJJ Manufacturing Lot Number Syww9001 Intel Finished Process Order FPO number Country Assy plant Country of Origin Topside fields not to scale Diameter of Pin 1 mark is 70 mils...

Page 230: ... Ordering Information Table 157 and Figure 60 provide IXF1104 MAC product ordering information Table 157 Product Information Product Number Revision Package Type RoHS Compliant HFIXF1104CE B0 B0 CBGA No WFIXF1104CE B0 B0 CBGA Yes HPIXF1104BE B01 B0 PBGA No NOTE 1 Please contact your field sales representative for detailed information on the FC PBGA package ...

Page 231: ...ion xn 2 Alphanumeric characters Temperature Range A Ambient 0 550 C C Commercial 0 700 C E Extended 40 850 C Internal Package Designator L LQFP P PLCC N DIP Q PQFP H QFP T TQFP B BGA C CBGA E TBGA K HSBGA BGA with heat slug Product Code xxxxx 3 5 Digit alphanumeric IXA Product Prefix LXT PHY layer device IXE Switching engine IXF Formatting device MAC Framer IXP Network processor Intel Package Des...

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