Volume 2, Part 2: Firmware Overview
2:623
Firmware Overview
13
Itanium-based systems make use of several firmware components: Processor
Abstraction Layer (PAL), System Abstraction Layer (SAL), Unified Extensible Firmware
Interface (UEFI) and Advanced Configuration and Power Interface (ACPI).
The PAL and SAL components work together to handle the reset abort event. The reset
abort handling performs processor and system initialization for operating system (OS)
boot and provides an API to the operating system loader. The PAL and SAL firmware
layers work together to handle machine check aborts (MCA), initialization events
(INIT), and platform management interrupt (PMI) handling. All firmware components
also provide runtime procedure calls to abstract processor and platform functions that
may vary across implementations.
This chapter will provide an overview of the firmware components and how the
firmware components interact with each other as well as with the operating system. For
the full architecture specifications of the PAL firmware please refer to
“Processor Abstraction Layer.”
For full architecture specifications on SAL, UEFI and ACPI
firmware components please refer to
Section 1.2, “Related Documents” on page 2:505
.
The PAL layer is developed by Intel Corporation and delivered with the processor. The
SAL, UEFI and ACPI firmware is developed by the platform manufacturer and provide a
means of supporting value added platform features from different vendors.
The interaction of the various functional firmware blocks with the processor, platform
and operating system is shown in
Figure 13-1, “Firmware Model” on page 2:624
13.1
Processor Boot Flow Overview
13.1.1
Firmware Boot Flow
Upon detection of a reset event on a processor based on the Itanium architecture,
execution begins at an architected entry point inside of PAL. This PAL code will verify
the integrity of the PAL code and may perform some basic processor testing. PAL will
then branch to an entry point within the SAL firmware. This first branch to SAL is to
determine if a firmware update is needed requiring re-programming of the firmware
code. If no firmware update is needed SAL will branch back to PAL.
PAL now performs additional processor testing and initialization. These first processor
tests are performed without platform memory. PAL indicates the outcome of the testing
and branches to an entry point within SAL firmware for the second time. SAL will now
begin platform testing and initialization. The exact division of work between SAL and
UEFI from that point on is platform implementation dependent. It is required that the
SAL runtime services, the UEFI boot and runtime services, and the ACPI tables and
control methods be exposed to the operating systems for correct operation.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...