Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

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Volume 2, Part 2: Performance Monitoring Support 2:619
Performance Monitoring Support 12
Processors based on the Itanium architecture include a minimum of four performance
counters which can be programmed to count processor events. These event counts can
be used to analyze both hardware and software performance. Performance counters
can be configured to generate a counter overflow interrupt. This interrupt can be used
for event- or time-based profiling. For hot-spot analysis of running code, performance
monitor interrupts can be used to create a profile of frequently occurring instruction
pointers (IP). Another common use of event counts is to compute processor
performance metrics such as cycles per instructions (CPI), the current branch, cache or
TLB miss rates, etc.
The Itanium architecture provides architected support for context switching of
performance monitors by an Itanium architecture-based operating system. If supported
by the operating system, this allows performance counter events to be broken down
per thread or per process which is important for effective performance tuning of
Itanium architecture-based applications.
The remainder of this chapter reviews the architected performance monitoring
mechanisms. It also discusses the Itanium architecture-based operating system
support needed for two monitoring usage models: per process/thread and system-wide
event monitoring.
12.1 Architected Performance Monitoring Mechanisms
As defined in Section 7.2, “Performance Monitoring” on page 2:155 , processors based
on the Itanium architecture provide a minimum of four generic performance counter
pairs (PMC/PMD[4..7]). The performance monitor control (PMC) registers are used to
select the event to be counted, and to define under what conditions the event should
qualify for being counted (for details refer to
Section 7.2.1, “Generic Performance
Counter Registers” on page 2:156 ). The performance monitor data (PMD) registers
contain the event count or data.
The PMC/PMD registers can only be written by privileged software (PSR.cpl must be
zero). A counter can be configured as a “privileged” counter or a “user-level” counter by
setting of the PMC[i].pm bit. Privileged counters can only read at privilege level 0, while
user-level counters can by read by user mode code (unless the operating system has
explicitly disabled the user-level monitor reads using PSR.sp).
Once the PMC/PMD registers have been configured, counting is enabled and disabled by
setting bits in the PSR. User-level counters can be controlled at user-level using the
rum and sum instructions to toggle PSR.up. Privileged counters are controlled by
privileged software using the rsm, ssm, mov from/to PSR instructions to toggle PSR.pp.
Counting for all counters is further controlled by the PMC[0] freeze bit. When PMC[0].fr
is 0, all counters are disabled. When PMC[0].fr is 1, counting is enabled based on
PMC[i].pm, PSR.pp and PSR.up. For more details on controlling of the performance
monitors please refer to
Section 7.2.1, “Generic Performance Counter Registers” on
page 2:156 .