Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 790 / 1898

2:542 Volume 2, Part 2: Interruptions and Serialization
“Interruption Vector Descriptions” for details. Software can use the instruction
bundle information for debug and emulation purposes.
No other architectural state is modified when an interruption occurs. Note that only IIP,
IPSR, ISR, and IFS are written by all interruptions (assuming PSR.ic is 1 at the time of
interruption); the other interruption control registers are only written by certain
interruptions, and their values are undefined otherwise. For details on which faults
update which interruption resources refer to
Chapter 8, “Interruption Vector
Descriptions” and Chapter 9, “IA-32 Interruption Vector Descriptions.”
3.3.3 Resource Serialization of Interrupted State
As defined in Section 3.2, “Serialization” on page 2:17 , Itanium control register
updates do not take effect until software explicitly serializes the processor’s data or
instruction stream with a
srlz.d
or a
srlz.i
instruction, respectively. Control register
updates that change a control register’s value and that have not yet been serialized are
termed “in-flight.” Refer to
Section 3.2.3, “Definition of In-flight Resources” on
page 2:19 for a precise definition.
When an interruption is delivered and before execution begins in the interruption
handler, the processor hardware automatically performs an instruction and data
serialization on all "in-flight" resources. As described in
Section 3.3.1 and Section 3.3.2
above, the following resources determine the execution environment of the interruption
handler:
• CR[IVA] – determines new IP
• CR[DCR].be – determines new value of PSR.be
• CR[DCR].pp – determines new value of PSR.pp
• PSR.ic – determines whether interruption collection is enabled
• RR[7:0] – determines new value of CR[ITIR] and CR[IHA]
• CR[PTA] – determines new value of CR[IHA]
Although these resources are guaranteed to be serialized prior to interruption handler
execution, there is no guarantee that they will be serialized prior to the determination
of the handler's execution environment. If there is a value in-flight for any of these
resources at the time of interruption delivery, either the old or new value may be used
to generate the values of IP, PSR, CR[ITIR] and CR[IHA] seen by the handler.
As a result, if the handler requires the latest value of the listed resources to determine
its execution environment, software must ensure that external interrupts are disabled
and that no instruction or data references will take an exception until the resource
updates have been appropriately serialized. Typically, the code toggling these resources
is mapped by an instruction translation register to avoid TLB related faults.
Note that CR[IPSR] is guaranteed to get the latest value of the PSR on an interruption,
even if there are PSR updates in-flight that have not been previously serialized by
software.