Volume 2, Part 1: Processor Abstraction Layer
2:487
Table 11-121. State Requirements for PSR for PAL Virtualization Services
PSR Bit
Description
Value
be
big-endian memory access enable
-
a
a. PAL services can be called with PSR.be bit equal to 0 or 1. The behavior is undefined if PSR.be setting does
not match the
be
parameter during PAL_VP_INIT_ENV. See
“PAL_VP_INIT_ENV – PAL Initialize Virtual
Environment (268)” on page 2:478
for details.
up
user performance monitor enable
-
ac
alignment check
-
mfl
floating-point registers f2-f31 written
-
mfh
floating-point registers f32-f127 written
-
ic
interruption state collection enable
0
b
b. Most PAL services are invoked with PSR.ic equal to 0.
-
c
i
interrupt enable
0
pk
protection key validation enable
-
dt
data address translation enable
1
dfl
disabled FP register f2 to f31
-
dfh
disabled FP register f32 to f127
-
sp
secure performance monitors
-
pp
privileged performance monitor enable
-
di
disable ISA transition
-
si
secure interval timer
-
db
debug breakpoint fault enable
0
lp
lower-privilege transfer trap enable
-
tb
taken branch trap enable
0
rt
register stack translation enable
1
cpl
current privilege level
0
is
instruction set
0
mc
machine check abort mask
-
it
instruction address translation enable
1
id
instruction debug fault disable
-
da
data access and dirty-bit fault disable
-
dd
data debug fault disable
-
ss
single step trap enable
0
ri
restart instruction
-
ed
exception deferral
-
bn
register bank
-
d
0
e
ia
instruction access-bit fault disable
-
vm
processor virtualization
0
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...