2:418
Volume 2, Part 1: Processor Abstraction Layer
PAL_MC_ERROR_INFO
Reg_File_Check Return Format:
The reg_file_check return format is returned in
error_info
when the user requests information on any of the registers as specified in the
level_index
input argument. The reg_file_check return format is a bit-field that is
described in
and
. When the reg_file_check return format is
returned, the target address, the requester identifier and the responder identifier will
always be invalid.
rq
61
Requester identifier: This bit is set to one to indicate that a valid requester identifier has
been logged.
rp
62
Responder identifier: This bit is set to one to indicate that a valid responder identifier has
been logged.
pi
63
Precise instruction pointer. This bit is set to one to indicate that a valid precise instruction
pointer has been logged.
Figure 11-23. reg_file_check Layout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
rnv
reg_num
op
id
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
pi
rsvd
mcc pv
pl
iv is
reserved
Table 11-93. reg_file_check Fields
Field
Bits
Description
id
3:0
Register file identifier:
0 – unknown/unclassified
1 – General register (bank1)
2 – General register (bank 0)
3 – Floating-point register
4 – Branch register
5 – Predicate register
6 – Application register
7 – Control register
8 – Region register
9 – Protection key register
10 – Data breakpoint register
11 – Instruction breakpoint register
12 – Performance monitor control register
13 – Performance monitor data register
All other values are reserved
op
7:4
Identifies the operation that caused the machine check
0 – unknown
1 – read
2 – write
All other values are processor specific
reg_num
14:8
Identifies the register number that was responsible for generating the machine check
rnv
15
Specifies if the
reg_num
field is valid
reserved
53:16
Reserved
is
54
Instruction set. If this value is set to zero, the instruction that generated the machine
check was an Intel Itanium instruction. If this bit is set to one, the instruction that
generated the machine check was IA-32 instruction.
iv
55
The
is
field in the reg_file_check parameter is valid.
Table 11-92. bus_check Fields (Continued)
Field
Bits
Description
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...