Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 662 / 1898

2:414 Volume 2, Part 1: Processor Abstraction Layer
PAL_MC_ERROR_INFO
instruction pointer available for logging on the second error. If there is, it makes
sub-sequent calls with
err_type_index equal to 9, 10, 11, and/or 12 depending on
which valid bits are set. The caller continues incrementing the err_type_index value in
this fashion until the inc_err_type return value is zero.
As shown in Table 11-89 , the information returned in error_info varies based on which
structure information is being requested on. The next sections describe the error_info
return format for the different structures.
Cache_Check Return Format : The cache check return format is returned in
error_info when the user requests information on any instruction or data/unified caches
in the level_index input argument. The cache_check return format must be used to
report errors in cacheable transactions. These errors may also be reported using the
bus_check return format if the bus structures can detect these errors. The cache_check
return format is a bit-field that is described in
Figure 11-20 and Table 11-90 .
Figure 11-20. cache_check Layout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hlth rsvd dp rv wiv way mv mesi ic dc tl dl rsvd level op
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
pi rp rq tv mcc pv pl iv is rsvd index
Table 11-90. cache_check Fields
Field Bits Description
op 3:0 Type of cache operation that caused the machine check:
0 – unknown or internal error
1 – load
2 – store
3 – instruction fetch or instruction prefetch
4 – data prefetch (both hardware and software)
5 – snoop (coherency check)
6 – cast out (explicit or implicit write-back of a cache line)
7 – move in (cache line fill)
All other values are reserved.
level 5:4 Level of cache where the error occurred. A value of 0 indicates the first level of cache.
rsvd 7:6 Reserved
dl 8 Failure located in the data part of the cache line.
tl 9 Failure located in the tag part of the cache line.
dc 10 Failure located in the data cache
ic 11 Failure located in the instruction cache
mesi 14:12 0 – cache line is invalid.
1 – cache line is held shared.
2 – cache line is held exclusive.
3 – cache line is modified.
All other values are reserved.
mv 15 The mesi field in the cache_check parameter is valid.
way 20:16 Failure located in the way of the cache indicated by this value.
wiv 21 The way and index field in the cache_check parameter is valid.
rsvd 22 Reserved
dp 23 An uncorrectable (typically multiple-bit) error was detected and data was poisoned for the
corresponding cache line, without any corrupted data being consumed (i.e., no corrupted
data has been copied to processor registers).