Volume 2, Part 1: Interruption Vector Descriptions
2:205
Name
Lower-Privilege Transfer Trap vector (0x5e00)
Cause
Two trapping conditions transfer control to this vector:
• An attempt is made to transfer control to an unimplemented address, resulting in
either an Unimplemented Instruction Address trap or an Unimplemented Instruction
Address fault.
See “Unimplemented Address Bits” on page 2:73.
• The PSR.lp bit is 1, and a branch lowers the privilege level.
IA-32 instructions can not raise this trap.
Interruptions on this vector:
Unimplemented Instruction Address fault
Unimplemented Instruction Address trap
Lower-Privilege Transfer trap
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
for a detailed description.
Note:
Please see
“Interruption Instruction Bundle Pointer (IIP – CR19)” on page 2:37
for a further clarification of the IIP value for an unimplemented instruction
address trap.
IIB0, IIB1 – If implemented, for Lower-Privilege Transfer traps, the IIB registers
contain the instruction bundle pointed to by IIPA. The IIB registers are undefined for
Unimplemented Instruction Address faults and traps. Please refer to
“Interruption Instruction Bundle Registers (IIB0-1 – CR26, 27)” on page 2:42
for
details on the IIB registers.
ISR – For Unimplemented Instruction Address trap and Lower-Privilege Transfer trap,
the ISR.ei bits are set to indicate which instruction caused the exception, and the
ISR.code contains a bit vector (see
) for all traps which
occurred in the just-executed instruction.
For Unimplemented Instruction Address fault ISR.fp_trap_code is set to 0.
The defined ISR bits are specified below.
If this vector was entered for an Unimplemented Instruction Address fault:
IFA – Faulting unimplemented instruction address
If this vector was entered for an Unimplemented Instruction Address trap:
If this vector was entered for a Lower-Privilege Transfer trap:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0 0 1 0 0 0 0
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0
0
ri
0 ni ir 0 0 0 0 0 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
fp trap code
0 0 1 ss tb lp fp
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0
0
ei
0 ni ir 0 0 0 0 0 0
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...