2:152
Volume 2, Part 1: Debugging and Performance Monitoring
reference that matches the parameters specified by the IBR registers results in an
IA_32_Exception(Debug) fault. If PSR.id is 1 or EFLAG.rf is 1, IA-32 Instruction
Debug faults are disabled for one instruction. The successful execution of an IA-32
instruction clears the PSR.id and EFLAG.rf bits.
•
Data Debug faults
– When PSR.db is 1, any Itanium data memory reference that
matches the parameters specified by the DBR registers results in a Data Debug
fault. Data Debug faults are only reported if the qualifying predicate is true. Data
Debug faults can be deferred on speculative loads by setting DCR.dd to 1. If PSR.dd
is 1, Data Debug faults are disabled for one instruction or one mandatory RSE
memory reference. When PSR.db is 1, any IA-32 data memory reference that
matches the parameters specified by the DBR registers results in a
IA_32_Exception(Debug) trap. IA-32 data debug events are traps, not faults as
defined for the Itanium instruction set. The reported trap code returns the match
status of the first 4 DBR registers that matched during the execution of the IA-32
instruction. See
“IA-32 Trap Code” on page 2:213
for trap code details. Zero, one or
more DBR registers may be reported as matching.
7.1.1
Data and Instruction Breakpoint Registers
Instruction or data memory addresses that match the Instruction or Data Breakpoint
Registers (IBR/DBR) shown in
and
result in an
Instruction or Data Debug fault. IA-32 Instruction or data memory addresses that
match the Instruction or Data Breakpoint Registers (IBR/DBR) result in an
IA_32_Exception(Debug) fault or trap. Even numbered registers contain breakpoint
addresses, odd registers contain breakpoint mask conditions. At least 4 data and 4
instruction register pairs are implemented on all processor models. Implemented
registers are contiguous starting with register 0.
When executing Itanium instructions, instruction and data memory addresses
presented for matching are always in the implemented address space. Programming an
unimplemented physical address into an IBR/DBR guarantees that physical addresses
presented to the IBR/DBR will never match. Similarly, programming an unimplemented
virtual address into an IBR/DBR guarantees that virtual addresses presented to the
IBR/DBR will never match.
Figure 7-1.
Data Breakpoint Registers (DBR)
63 62 61 60 59
56 55
0
DBR
0,2,4..
addr
DBR
1,3,5..
r w
ig
plm
mask
1 1
2
4
56
Figure 7-2.
Instruction Breakpoint Registers (IBR)
63 62 61 60 59
56 55
0
IBR
0,2,4..
addr
IBR
1,3,5..
x
ig
plm
mask
1
3
4
56
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...