Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1767 / 1898

Volume 4: IA-32 SSE Instruction Reference 4:465
4.5 SSE Registers
The Intel SSE architecture provides eight 128-bit general purpose registers, each of
which can be directly addressed. These registers are new state, and require support
from the operating system to use them.
The SSE registers can hold packed 128-bit data. The SSE instructions access the SSE
registers directly using the registers names XMM0 to XMM7 (
Figure 4-2 ).
SSE registers can be used to perform calculation on data. They cannot be used to
address memory; addressing is accomplished by using the integer registers and
existing IA addressing modes.
The contents of SSE registers are cleared upon reset.
There is a new control/status register MXCSR which is used to mask/unmask numerical
exception handling, to set rounding modes, to set flush-to-zero mode, and to view
status flags.
4.6 Extended Instruction Set
The Intel SSE architecture supplies a rich set of instructions that operate on either all or
the least significant pairs of packed data operands, in parallel. The packed instructions
operate on a pair of operands as shown in
Figure 4-3 while scalar instructions always
operate on the least significant pair of the two operands as shown in Figure 4-4 ; for
scalar operations, the three upper components from the first operand are passed
through to the destination. In general, the address of a memory operand has to be
aligned on a 16-byte boundary for all instructions, except for unaligned loads and
stores.
Figure 4-2. SSE Register Set
XMM7
XMM6
XMM5
XMM4
XMM3
XMM2
XMM1
XMM0