Volume 1, Part 2: Memory Reference
1:147
Memory Reference
3
3.1
Overview
Memory latency is a major factor in determining the performance of integer
applications. In order to help reduce the effects of memory latency, the Itanium
architecture explicitly supports software pipelining, large register files, and
compiler-controlled speculation. This chapter discusses features and optimizations
related to compiler-controlled speculation. See
Chapter 5, “Software Pipelining and
for a complete description of how to use software pipelining.
The early sections of this chapter review non-speculative load and store in the Itanium
architecture, and general concepts and terminology related to data dependencies. The
concept of speculation is then introduced, followed by discussions and examples of how
speculation is used. The remainder of this chapter describes several important
optimizations related to memory access and instruction scheduling.
3.2
Non-speculative Memory References
The Itanium architecture supports non-speculative loads and stores, as well as explicit
memory hint instructions.
3.2.1
Stores to Memory
Itanium integer store instructions can write either 1, 2, 4, or 8 bytes and 4, 8, or 10
bytes for floating-point stores. For example, a
st4
instruction will write the first four
bytes of a register to memory.
Although the Itanium architecture uses a little endian memory byte order by default,
software can change the byte order by setting the big endian (be) bit of the user mask
(UM).
3.2.2
Loads from Memory
Itanium integer load instructions can read either 1, 2, 4, or 8 bytes from memory
depending on the type of load issued. Loads of 1, 2, or 4 bytes of data are
zero-extended to 64-bits prior to being written into their target registers.
Although loads are provided for various data types, the basic data type is the quadword
(8 bytes). Apart from a few exceptions, all integer operations are on quadword data.
This can be particularly important when dealing with signed integers and 32-bit
addresses, or any addresses that are shorter than 64 bits.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...