Intel Itanium 9010, Manual

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100 Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
Signals Reference
A.1.41 INT (I)
INT is the 8259-compatible Interrupt Request signal which indicates that an external
interrupt has been generated. The interrupt is maskable. The processor vectors to the
interrupt handler after the current instruction execution has been completed. An
interrupt acknowledge transaction is generated by the processor to obtain the interrupt
vector from the interrupt controller.
The LINT[0] pin can be software configured to be used either as the INT signal or
another local interrupt.
A.1.42 IP[1:0]# (I)
The ID Parity (IP[1:0]#) signals are driven on the second clock of the Deferred Phase
by the deferring agent. IP0# protects the IDa[9:0]# and IDS# signals for the first
clock, and IP[1]# protects the IDb[9:2, 0]# and IDS# signals on the second clock.
A.1.43 LEN[2:0]# (I/O)
The Data Length (LEN[2:0]#) signals are transmitted using REQb[2:0]# signals by the
requesting agent in the second clock of Request Phase. LEN[2:0]# defines the length of
the data transfer requested by the requesting agent as shown in
Table A-9 . The
LEN[2:0]#, HITM#, and RS[2:0]# signals together define the length of the actual data
transfer.
A.1.44 LINT[1:0] (I)
LINT[1:0] are local interrupt signals. These pins are disabled after RESET#. LINT[0] is
typically software configured as INT, an 8259-compatible maskable interrupt request
signal. LINT[1] is typically software configured as NMI, a non-maskable interrupt.Both
signals are asynchronous inputs.
A.1.45 LOCK# (I/O)
LOCK# is no connect and is ignored in the processor system environment.
Table A-9. Length of Data Transfers
LEN[2:0]# Length
000 0 – 8 bytes
001 16 bytes
010 32 bytes
011 64 bytes
100 128 bytes
101 Reserved
110 Reserved
111 Reserved