35
Specification Update
AAU59.
VM Exits Due to "NMI-Window Exiting" May Be Delayed by One
Instruction
Problem:
If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a
VM exit with exit reason "NMI window" should occur before execution of any instruction
if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of
events by STI. If VM entry is made with no virtual-NMI blocking but with blocking of
events by either MOV SS or STI, such a VM exit should occur after execution of one
instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed
by one additional instruction.
Implication:
VMM software using "NMI-window exiting" for NMI virtualization should generally be
unaffected, as the erratum causes at most a one-instruction delay in the injection of a
virtual NMI, which is virtually asynchronous. The erratum may affect VMMs relying on
deterministic delivery of the affected VM exits.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU60.
The Memory Controller tTHROT_OPREF Timings May be Violated
During Self Refresh Entry
Problem:
During self refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING
CSR).
Implication:
The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU61.
VM Exits Due to EPT Violations Do Not Record Information About Pre-
IRET NMI Blocking
Problem:
With certain settings of the VM-execution controls VM exits due to EPT violations set bit
12 of the exit qualification if the EPT violation was a result of an execution of the IRET
instruction that commenced with non-maskable interrupts (NMIs) blocked. Due to this
erratum, such VM exits will instead clear this bit.
Implication:
Due to this erratum, a virtual-machine monitor that relies on the proper setting of bit
12 of the exit qualification may deliver NMIs to guest software prematurely.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU62.
Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
Problem:
When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication:
Multiple counter overflow interrupts may be unexpectedly generated.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
