Diagram label
Description
• Parallel loopback with external VCXO
— Due to the limitation on Nextera daughter card which only has 297 MHz,
this design example is having the TX PLL reference clock connected to the
297 MHz clock.
— Use a minimum clock frequency of 148.5 MHz to meet jitter performance
specification.
• Serial loopback
— For this design, the TX PLL refclock is configured to generate clock for
integer frame rate.
— Use a minimum clock frequency of 148.5 MHz to meet jitter performance
specification.
RX CDR refclock
Transceiver clock data recovery (CDR) reference clock, of any frequency divisible
by the transceiver for that data rate. Only a single reference clock frequency
which the recommendation is 148.5 MHz is required to support both integer and
fractional frame rate. It must be a free running clock which are connected from a
dedicated transceiver reference clock pin to the input clock port of Reference and
System PLL Clocks IP, before connecting the corresponding output port to SDI
top module.
Note: Do not share the TX PLL reference clock with the RX transceiver reference
clock for a parallel loopback design. In parallel loopback designs, the TX PLL
clock is tuned to match the RX recovered clock frequency.
GPIO clock / RX coreclk / DR clocks
SDI RX core reference clock which must be a free running clock depending on
the RX core clock Frequency parameter value.
All generated design examples have this clock set to 148.5 MHz regardless of the
GUI option because of the development kit's default limited clock frequency
option.
TX PLL / RX CDR link clock
Output ports from Reference and System PLL Clocks IP. These clocks are
supposedly to be connected to the transceiver reference clock input of F-tile
Direct PHY IP.
System PLL output link clock
Output ports from Reference and System PLL Clocks IP. These clocks are
supposedly to be connected to the system PLL clock input of F-tile Direct PHY IP.
The minimum System PLL output frequency for each SDI mode is given below:
SDI mode
Minimum System PLL output freq
HD-SDI single rate
150 MHz
3G-SDI single rate
300 MHz
12G-SDI single rate
600 MHz
TX/RX transceiver clkout2
Recovered clock from transceiver
For SD video standard,
• 148.5 MHz
For HD video standard,
• 74.25 MHz when receiving integer frame rate.
• 74.1758 MHz when receiving fractional frame rate
For 3G/6G/12G video standard,
• 148.5 MHz when receiving integer frame rate.
• 148.35 MHz when receiving fractional frame rate
TX/RX transceiver clkout
This is the div2 clock from System PLL output clock which the F-tile PMA/FEC
Direct PHY IP is operating in. This clock is supposedly to be connected to a
DCFIFO which is interfacing between SDI II IP and the Direct PHY IP.
Note:
Intel recommends you not to share TX PLL reference clock with RX transceiver
reference clock for a parallel loopback design because TX PLL clock is going to be
tuned to match RX recovered clock frequency.
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel
®
Agilex
™
FPGA IP Design Example User Guide
26
