Common Block
Description
SDI mode
Minimum System PLL output
frequency
HD-SDI single rate
150 MHz
3G-SDI single rate
300 MHz
12G-SDI single rate
600 MHz
Device Initialization
This module contains Reset Release Intel FPGA IP to provide a known initialized
state for system logic to begin operation. The module also includes a reset delay
block to further delay the signal status from the IP for a safer operation.
For more information, refer to Intel Agilex Reset Release Intel FPGA IP in Intel
Agilex Configuration User Guide.
Related Information
Intel Agilex Configuration User Guide
More information about Intel Agilex Reset Release IP.
2. Design Example Detailed Description
710496 | 2022.01.28
F-Tile SDI II Intel
®
Agilex
™
FPGA IP Design Example User Guide
21
