Intel E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core Processor, Datasheet

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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 93
Features
Notes:
1. The specification is at T
CASE
= 50°C and nominal V
CC
. The VID setting represents the maximum expected
VID while running in HALT state.
2. This specification is characterized by design.
3. Processors running in the lowest bus ratio will enter the HALT state when the processor has executed the
HALT and MWAIT instruction since the processor is already in the lowest core frequency and voltage
operating point. Values represent SKUs with Extended HALT state (30 W) and without Extended HALT state
(34 W).
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will first transition the VID to the original
value and then change the bus to core frequency ratio back to the original value.
Table 7-2. Extended HALT Maximum Power
Symbol Parameter Min Typ Max Unit Notes
P
EXTENDED_HALT
Quad-Core Intel®
Xeon® Processor
E5300 Series
Extended HALT
State Power
30/34 W 1,2,3
P
EXTENDED_HALT
Quad-
Core Intel® Xeon®
Processor X5300
Series
Extended HALT
State Power
50 W 1,2
Figure 7-1. Stop Clock State Machine
Extended HALT or HALT State
BCLK running
Snoops and interrupts allowed
Normal State
Normal execution
Extended HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Stop Grant State
BCLK running
Snoops and interrupts allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
STPCLK#
Asserted STPCLK#
De-asserted
S
TP
C
LK
#
A
ss
er
te
d
S
TP
C
LK
#
D
e-
as
se
rte
d
Snoop Event Occurs
Snoop Event Serviced
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Stop Grant Snoop State
BCLK running
Service snoops to caches