Intel Cyclone 10 GX User Manual Download Page 6

 

4.

 

Only execute step 4 if your C10 GX Development Kit Board belongs to 1

st

 prototype build with board serial 

number within 0000001-0000030 else skip to step 5.

 For 1

st

 prototype board, by default after power up 

the development kit board, the programmable clock generator (Si5332) used for the transceiver channel 

in this design is disabled. Do the following to enable and configure the output clock frequencies correctly 

 

a. Download and unzip 

“Kit Collateral

.zip

” 

design package from below link 

https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html

 

b. Launch Quartus software first then run the ClockController.exe from  

cyclone-10-gx-kit-collateral\examples\board_test_system 

c. By default, the Clock Controller GUI should look like Figure 4 

 

            Figure 4. Default Clock Controller GUI for Si5332

 

 

d. Click the “Import” button in Clock Controller GUI and select the “

U64-Registers.txt

 in cyclone-10-gx-kit-

collateral\examples\board_test_system folder to configure the output clock frequencies 

 

 

 

Summary of Contents for Cyclone 10 GX

Page 1: ...holders as described at www altera com common legal html Intel warrants performance of its semiconductor products to current specifications in accordance with Intel s standard warranty but reserves th...

Page 2: ...nt 3 Theory of Operation 3 How to Setup the Development Kits for XCVR Loopback Test 4 How to Reconstruct and Run the Reference Design 5 Hardware setup 5 XCVR Channel Loopback Test Run Procedure 8 Conc...

Page 3: ...25Gbps XCVR duplex channel Requirement The reference design requires the following hardware and software to run the hardware test Quartus Prime Software Version 17 1 1 Pro Edition Cyclone 10 GX Develo...

Page 4: ...e off user to manually perform on board external loopback via FPGA FMC loopback card Loopback mode serial loopback activate serial loopback path within XCVR PMA block How to Setup the Development Kits...

Page 5: ...tus software 2 Perform full compilation with the Quartus design 3 Carry out following steps to reduce the JTAG frequency from default 24MHz to 16MHz to avoid JTAG connection issue a Launch NIOS II com...

Page 6: ...orrectly a Download and unzip Kit Collateral zip design package from below link https www altera com products boards_and_kits dev kits altera cyclone 10 gx development kit html b Launch Quartus softwa...

Page 7: ...5 Clock Controller GUI for Si5332 after Successful Configuration f Close the Clock Controller application g Note that you would need to reconfigure the Si5332 using step 4 b 4 f each time the Developm...

Page 8: ...e programmed SOF file 4 Toolkit should initialize one XCVR duplex channel as shown in Figure 6 Figure 6 XCVR channel initialization in toolkit 5 Click the XCVR channel under Link Alias then click on C...

Page 9: ...t 7 Procedure to test External On Board Loopback with FMC Loopback Card plugged on board a Set Loopback Mode to Off as shown in Figure 8 Figure 8 Passing test run with External On Board Loopback Mode...

Page 10: ...I if necessary d Follow test run procedure to bring up XCVR toolkit e Set Loopback Mode to Off as shown in Figure 9 Figure 9 Failing test run with External On Board Loopback Mode f Click Start button...

Page 11: ...imple NativePHY IP design References Intel Cyclone 10 GX Transceiver PHY User Guide https www altera com documentation hki1486507600636 html Intel Cyclone 10 GX Development Kit Board Website https www...

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