Errata
Specification Update
33
Implication:
When this erratum occurs, system and cache memory may be corrupted.
Workaround:
While there is no workaround to prevent the second line from being corrupted,
avoiding tight data sharing and tight spin loops will reduce the possibility of this
erratum occurring. Tight spin loops can be avoided by inserting the PAUSE instruction
into the loop.
Status:
For the steppings affected, see the
Summary Tables of Changes.
7.
Overlap of MTRRs with the Same Memory Type Results in a Type of
Uncacheable (UC)
Problem:
If two or more variable memory type range registers overlap, both with memory type
X (where X is WB, WT, or WC), the resulting memory type for the overlap range will
be UC instead of the more logical memory type X.
Implication:
When this erratum occurs, a potentially significant performance decrease may occur
for accesses to these memory ranges since the memory type has been translated to
UC.
Workaround:
Intel does not support the overlapping of any two or more MTRRs unless one of
them is of UC memory type. Ensure that the system BIOS does not create
overlapping memory ranges.
Status:
For the steppings affected, see the
Summary Tables of Changes.
8.
FSW May Not Be Completely Restored after Page Fault on FRSTOR or
FLDENV Instructions
Problem:
If the FPU operating environment or FPU state (operating environment and register
stack) being loaded by an FLDENV or FRSTOR instruction wraps around a 64-KB or 4-
GB boundary and a page fault (#PF) or segment limit fault (#GP or #SS) occurs on
the instruction near the wrap boundary, the upper byte of the FPU status word (FSW)
might not be restored. If the fault handler does not restart program execution at the
faulting instruction, stale data may exist in the FSW.
Implication:
When this erratum occurs, stale data will exist in the FSW.
Workaround:
Ensure that the FPU operating environment and FPU state do not cross 64-KB or
4-GB boundaries. Alternately, ensure that the page fault handler restarts program
execution at the faulting instruction after correcting the paging problem.
Status:
For the steppings affected, see the
Summary Tables of Changes.
9.
The Processor Signals Page-Fault Exception (#PF) Instead of
Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B
Instruction
Problem:
If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for
an unlocked CMPXCHG8B instruction, then #PF will be flagged.
Implication:
Software that depends on the Alignment Check Exception (#AC) before the Page-
Fault Exception (#PF) will be affected since #PF is signaled in this case.
