Intel BX80619I73960X, Datasheet

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4 Datasheet, Volume 1
4 Power Management .................................................................................................27
4.1 Advanced Configuration and Power Interface (ACPI) States Supported ......................27
4.1.1
System States........................................................................................27
4.1.2 Processor Package and Core States ...........................................................27
4.1.3 Integrated Memory Controller States .........................................................29
4.1.4 DMI2 / PCI Express* Link States...............................................................29
4.1.5 G, S, and C State Combinations................................................................30
4.2 Processor Core / Package Power Management .......................................................30
4.2.1
Enhanced Intel
®
SpeedStep
®
Technology ..................................................30
4.2.2 Low-Power Idle States.............................................................................31
4.2.3 Requesting Low-Power Idle States ............................................................32
4.2.4 Core C-states .........................................................................................32
4.2.4.1
Core C0 State ...........................................................................33
4.2.4.2 Core C1/C1E State ....................................................................33
4.2.4.3 Core C3 State ...........................................................................33
4.2.4.4 Core C6 State ...........................................................................33
4.2.4.5 Core C7 State ..........................................................................33
4.2.4.6 C-State Auto-Demotion .............................................................33
4.2.5 Package C-States ...................................................................................34
4.2.5.1
Package C0 ..............................................................................35
4.2.5.2 Package C1/C1E........................................................................35
4.2.5.3 Package C2 State ......................................................................36
4.2.5.4 Package C3 State ......................................................................36
4.2.5.5 Package C6 State ......................................................................36
4.2.6 Package C-State Power Specifications........................................................37
4.3 System Memory Power Management ....................................................................37
4.3.1
CKE Power-Down....................................................................................37
4.3.2 Self Refresh ...........................................................................................38
4.3.2.1
Self Refresh Entry .....................................................................38
4.3.2.2 Self Refresh Exit .......................................................................38
4.3.2.3 DLL and PLL Shutdown...............................................................38
4.3.3 DRAM I/O Power Management ..................................................................38
4.4 DMI2 / PCI Express* Power Management ..............................................................38
5 Thermal Management Specifications ........................................................................39
6 Signal Descriptions ..................................................................................................41
6.1 System Memory Interface ...................................................................................41
6.2 PCI Express* Based Interface Signals ...................................................................42
6.3 DMI2 / PCI Express* Port 0 Signals ......................................................................44
6.4 Platform Environment Control Interface (PECI) Signal.............................................44
6.5 System Reference Clock Signals ..........................................................................44
6.6 JTAG and TAP Signals.........................................................................................45
6.7 Serial VID Interface (SVID) Signals ......................................................................45
6.8 Processor Asynchronous Sideband and Miscellaneous Signals...................................46
6.9 Processor Power and Ground Supplies ..................................................................48
7 Electrical Specifications ...........................................................................................49
7.1 Processor Signaling ............................................................................................49
7.1.1
System Memory Interface Signal Groups....................................................49
7.1.2 PCI Express* Signals...............................................................................49
7.1.3 DMI2/PCI Express* Signals ......................................................................49
7.1.4 Platform Environmental Control Interface (PECI) .........................................49
7.1.4.1
Input Device Hysteresis .............................................................50
7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) .........................50
7.1.5.1
PLL Power Supply ......................................................................50
7.1.6 JTAG and Test Access Port (TAP) Signals....................................................51
7.1.7 Processor Sideband Signals ......................................................................51
7.1.8 Power, Ground and Sense Signals .............................................................51