Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification Download Page 59

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Specification Update, October 2009

Summary of Contents for BV80605001914AG - Processor - 1 x Xeon X3430

Page 1: ...Reference Number 322373 009 Intel Xeon Processor 3400 Series Specification Update May 2010 ...

Page 2: ...r a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology Intel Virtualization Technology Intel VT x and Intel Virtualization Technology for Directed I O Intel VT d...

Page 3: ...3 Specification Update Contents Revision History 5 Preface 6 Summary Tables of Changes 8 Identification Information 16 Errata 19 Specification Changes 55 Specification Clarifications 56 Documentation Changes 57 ...

Page 4: ...Contents 4 Specification Update ...

Page 5: ...n Processor X3430 S Spec Number SLBLJ Intel Xeon Processor L3426 S Spec Number SLBN3 Added Errata AAO110 AAO113 November 2009 004 Updated Errata AAO89 and AAO99 December 2009 005 Added Erratum AAO114 January 2010 006 Added Errata AAO115 and AAO116 February 2010 007 Added Erratum AAO17 March 2010 008 Added Errata AAO18 and AAO19 April 2010 009 Updated the Processor Identification Table to include I...

Page 6: ...01 Document Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Softwar...

Page 7: ...of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of th...

Page 8: ...s Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this document Status Doc Document change or update will be implemented Plan Fix This erratum may be fixed in a future steppi...

Page 9: ...t Intel Xeon processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions T Mobile Intel Pentium 4 processor M U 64 bit Intel Xeon processor MP with up to 8MB L3 cache V Mobile Intel Celeron processor on 13 micron process in Micro FCPGA package W Intel Celeron M processor X Intel Pentium M processor on 90nm process with 2 MB L2 cache and Intel processor A100 and A110 with 512 KB L2 cache Y In...

Page 10: ...sor and Intel Core 2 Extreme processor on 45 nm process AAA Intel Xeon processor 3300 series AAB Intel Xeon E3110 processor AAC Intel Celeron dual core processor E1000 series AAD Intel Core 2 Extreme processor QX9775 AAE Intel Atom processor Z5xx series AAF Intel Atom processor 200 series AAG Intel Atom processor N series AAH Intel Atom processor 300 series AAI Intel Xeon processor 7400 series AAJ...

Page 11: ...ytes May be Preempted AAO13 X No Fix General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit AAO14 X No Fix LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode AAO15 X No Fix MONITOR or CLFLUSH on the Local XAPIC s Address Space Results in Hang AAO16 X No Fix Corruption of CS Segment Register During RSM While Transitionin...

Page 12: ...o Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 AAO41 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur AAO42 X No Fix EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine AAO43 X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM AAO44 X No Fix API...

Page 13: ...s DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount AAO67 X No Fix Rapid Core C3 C6 Transitions May Cause Unpredictable System Behavior AAO68 X No Fix Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately AAO69 X No Fix A Page Fault May Not be Generated When the PS bit is set to 1 in a PML4E or PDPTE AAO70 X No Fix CPURESET Bit Does Not Get Cleared AAO71 X No Fix PHO...

Page 14: ...Temp May Cause System Hang in Package C6 State AAO94 X No Fix PECI Mailbox Commands During Package C6 Idle State Transitions May Result in Unpredictable Processor Behavior AAO95 X No Fix VMX Preemption Timer Does Not Count Down at the Rate Specified AAO96 X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 AAO97 X No Fix SVID and SID of Devices 8 and 16 onl...

Page 15: ...Across Cacheline Boundaries May Lead to Processor Livelock AAO116 X No Fix PCIe Link Bit Errors Present During L0s Entry May Cause the System to Hang During L0s Exit AAO117 X No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4 Gbyte Boundary in Code That Uses 32 Bit Address Size in 64 bit Mode AAO118 X No Fix IOTLB Invalidations Not Completing on Intel V...

Page 16: ... field of the Device ID register accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of that model See Table 1 for the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Number and Stepping ID value in the EAX register...

Page 17: ... GHz 2 Shared L3 Cache Size MB Notes 8 SLBPT X3480 B 1 106E5h 3 06 1333 4 core 3 33 3 core 3 33 2 core 3 60 1 core 3 73 8 1 3 4 5 6 SLBJH X3470 B 1 106E5h 2 93 1333 4 core 3 20 3 core 3 20 2 core 3 46 1 core 3 60 8 1 3 4 5 6 SLBJK X3460 B 1 106E5h 2 80 1333 4 core 2 93 3 core 2 93 2 core 3 33 1 core 3 46 8 1 3 4 5 6 SLBLD X3450 B 1 106E5h 2 66 1333 4 core 2 80 3 core 2 80 2 core 3 20 1 core 3 20 8...

Page 18: ... d enabled 7 This processor has TDP of 45 W 8 The core frequency reported in the processor brand string is rounded to 2 decimal digits For example core frequency of 3 4666 repeating 6 is reported as 3 47 in brand string Core frequency of 3 3333 is reported as 3 33 in brand string SLBLJ X3430 B 1 106E5h 2 40 1333 4 core 2 53 3 core 2 53 2 core 2 66 1 core 2 80 8 1 4 5 6 SLBN3 L3426 B 1 106E5h 1 86 ...

Page 19: ...rations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross page boundaries from WB WC memory types to UC WP WT memory types may start using an incorrect data size or may observe memory ordering violations Implication Upon crossing the page boundary the following may o...

Page 20: ...a non canonical address the address pushed onto the stack for this GP fault may not match the non canonical address that caused the fault Implication Operating systems may observe a GP fault being serviced before higher priority Interrupts and Exceptions Intel has not observed this erratum on any commercially available software Workaround None identified Status For the steppings affected see the S...

Page 21: ...ay issue a memory load before getting the DNA exception Workaround Code which performs loads from memory that has side effects can effectively workaround this behavior by using simple integer based load instructions when accessing side effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side effect memory Status For...

Page 22: ...m SMM System Management Mode the CPU will incorrectly update the LBR Last Branch Record and the BTS Branch Trace Store hence rendering their data invalid The corresponding data if sent out as a BTM on the system bus will also be incorrect Note This issue would only occur when one of the 3 above mentioned debug support facilities are used Implication The value of the LBR BTS and BTM immediately aft...

Page 23: ...n only occur if the IRET instruction is returning from CPL3 code to CPL3 code IRETs from CPL0 1 2 are not affected This erratum can occur if the EFLAGS value on the stack has the AC flag set and the interrupt handler s stack is misaligned In IA 32e mode RSP is aligned to a 16 byte boundary before pushing the stack frame Implication In IA 32e mode under the conditions given above an IRET can get a ...

Page 24: ...al boundary 0x00007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1 s Subsequent BTS and BTM operations which report the LBR will also be incorrect Implication LBR BTS and BTM may report incorrect information in the event of an exception interrupt Workaround None identified Status For the steppings affected s...

Page 25: ... to fill occupancy counter UNC_GQ_ALLOC RT_LLC_MISS Event 02H will provide erroneous results Implication The Performance Monitoring UNC_GQ_ALLOC RT_LLC_MISS event may count a value higher than expected The extent to which the value is higher than expected is determined by the frequency of the L3 address conflict Workaround None identified Status For the steppings affected see the Summary Tables of...

Page 26: ...r of events Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAO21 GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem During a GP General Protection Exception the processor pushes an error code on to the exception handler s stack If the segment selector descriptor straddles the canon...

Page 27: ...ug event signaling created by this erratum Status For the steppings affected see the Summary Tables of Changes AAO24 IA32_MPERF Counter Stops Counting During On Demand TM1 Problem According to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide the ratio of IA32_MPERF MSR E7H to IA32_APERF MSR E8H should reflect actual performance while TM1 or on dem...

Page 28: ...tion temperature and then Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR 1A0H bit 3 a subsequent re enable of Thermal Monitor will result in an artificial ceiling on the maximum core P state The ceiling is based on the core frequency at the time of Thermal Monitor disable This condition will only correct itself once the processor reaches its TCC activation temperature again Implic...

Page 29: ...l interrupts at the same or lower priority Workaround Any vector programmed into an LVT entry must have an ISR associated with it even if that vector was programmed as masked This ISR routine must do an EOI to clear any unexpected interrupts that may occur The ISR associated with the spurious vector does not generate an EOI therefore the spurious vector should not be used when writing the LVT Stat...

Page 30: ...ion Bits 53 50 of the IA32_VMX_BASIC MSR report that the WB write back memory type will be used but the processor may use a different memory type Workaround Software should ensure that the VMCS and referenced data structures are located at physical addresses that are mapped to WB memory type by the MTRRs Status For the steppings affected see the Summary Tables of Changes AAO35 B0 B3 Bits in DR6 Fo...

Page 31: ...ache line splits for optimization purposes may read excessive number of memory misalignment events Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAO38 Changing the Memory Type for an In Use Page Translation May Lead to Memory Ordering Violations Problem Under complex microarchitectural conditions if software changes the memory type for data being ac...

Page 32: ...ile counting down the current count reaches 1 at the same time that the processor thread begins a transition to a low power C state the xAPIC may generate two interrupts instead of the expected one when the processor returns to C0 Implication Due to this erratum two interrupts may unexpectedly be generated by an xAPIC timer event Workaround None identified Status For the steppings affected see the...

Page 33: ...ceived on the same internal clock that the ESR is being written as part of the write read ESR access flow The corresponding error interrupt will also not be generated for this case Implication Due to this erratum an incoming illegal vector error may not be logged into ESR properly and may not generate an error interrupt Workaround None identified Status For the steppings affected see the Summary T...

Page 34: ...to back writes that match MC_CHANNEL_ 0 1 _ADDR_MATCH the 2nd write will not have the error injected Implication The 2nd back to back write that matches MC_CHANNEL_ 0 1 _ADDR_MATCH will not have the ECC error properly injected Setting MC_CHANNEL_ 0 1 _ADDR_MATCH to a specific address will reduce the chance of being impacted by this erratum Workaround Only injecting errors to specific address shoul...

Page 35: ...a sleep state may not wake up to handle the broadcast IPI Intel has not observed this erratum with any commercially available software Workaround Use destination shorthand of 10B or 11B to send broadcast IPIs Status For the steppings affected see the Summary Tables of Changes AAO52 Faulting Executions of FXRSTOR May Update State Inconsistently Problem The state updated by a faulting FXRSTOR instru...

Page 36: ...rformance counter IA32_PMC0 4 C1H C4H may count at core frequency or not count at all instead of counting the programmed event Implication The Performance Monitor Counter IA32_PMCx may not properly count the programmed event Due to the requirements of the workaround there may be an interruption in the counting of a previously programmed event during the programming of a new event Workaround Before...

Page 37: ...atus For the steppings affected see the Summary Tables of Changes AAO58 EFLAGS Discrepancy on Page Faults and on EPT Induced VM Exits after a Translation Change Problem This erratum is regarding the case where paging structures are modified to change a linear address from writable to non writable without software performing an appropriate TLB invalidation When a subsequent access to that address b...

Page 38: ...re operation is not supported on the DRAM the memory controller will not enter self refresh if software has REF_2X_NOW bit 4 of the MC_CLOSED_LOOP CSR function 3 offset 84H set This scenario may cause the system to hang during C3 C6 entry Implication Failure to enter self refresh can delay C3 C6 power state transitions to the point that a system hang may result with CATERR being asserted REF_2X_NO...

Page 39: ...Status For the steppings affected see the Summary Tables of Changes AAO64 PSI Signal May Incorrectly be Left Asserted Problem When some of the cores in the processor are in C3 C6 state the PSI Power Status Indicator signal may incorrectly be left asserted when another core makes a frequency change request without changing the operating voltage Since this erratum results in a possible maximum core ...

Page 40: ...For the steppings affected see the Summary Tables of Changes AAO68 Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately Problem The performance monitor event INSTR_RETIRED Event C0H should count the number of instructions retired and MEM_INST_ RETIRED Event 0BH should count the number of load or store instructions retired However due to this erratum they may underco...

Page 41: ...g of the D1 and D2 Power States Problem The PCIe PMCSR Power Management Control and Status Register Device 3 4 5 6 Function 0 Offset E4H incorrectly allows the writing requesting of the D1 and D2 Power States in the Power State field bits 1 0 of PMCSR when these states are not supported Implication Given that the device does not support the D1 and D2 states attempts to write those states should ha...

Page 42: ...ored address range which is issued as uncacheable for example having the CR0 CD bit set may prevent subsequent writes from triggering the monitor hardware A write to the monitored address range which is issued as uncacheable may not trigger the monitor hardware and may prevent subsequent writes from triggering the monitor hardware Implication The MWAIT instruction will not exit the optimized power...

Page 43: ...additional instruction Implication VMM software using NMI window exiting for NMI virtualization should generally be unaffected as the erratum causes at most a one instruction delay in the injection of a virtual NMI which is virtually asynchronous The erratum may affect VMMs relying on deterministic delivery of the affected VM exits Workaround None identified Status For the steppings affected see t...

Page 44: ...etion Status For the steppings affected see the Summary Tables of Changes AAO84 VM Exits Due to EPT Violations Do Not Record Information About Pre IRET NMI Blocking Problem With certain settings of the VM execution controls VM exits due to EPT violations set bit 12 of the exit qualification if the EPT violation was a result of an execution of the IRET instruction that commenced with non maskable i...

Page 45: ...other performance counters Implication Multiple counter overflow interrupts may be unexpectedly generated Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAO88 LBRs May Not be Initialized During Power On Reset of the Processor Problem If a second reset is initiated during the power on processor reset cycle the LBRs Last Branch Records may not be prope...

Page 46: ...er an EIST transition T states C1E or Adaptive Thermal Throttling Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAO92 PECI GetTemp Reads May Return Invalid Temperature Data in Package C6 State Problem The PECI Platform Environment Control Interface GetTemp command may occasionally return incorrect temperature data Implication The temperature data re...

Page 47: ...ct mailbox response may result Implication The PECI mailbox commands are not reliable during processor package C6 idle state and may result in unpredictable processor behavior or incorrect PECI responses Workaround It is possible for the BIOS to contain a workaround for this erratum This workaround involves disabling PECI mailbox functions during package C6 idle state causing the processor to miss...

Page 48: ...ffected see the Summary Tables of Changes AAO97 SVID and SID of Devices 8 and 16 only implement bits 7 0 Problem Bits 15 8 of SVID Subsystem Vendor ID Offset 2CH and the SID Subsystem Device ID Offset 2EH of devices 8 and 16 are not implemented Only the lower bits 7 0 of these registers can be written to though the PCI e specification indicates that these are 16 bit registers Implication Only bits...

Page 49: ...TA and STORE_BLOCKS STA May Not Count Events Correctly Problem Performance Monitor Events STORE_BLOCKS NOT_STA and STORE_BLOCKS STA should only increment the count when a load is blocked by a store Due to this erratum the count will be incremented whenever a load hits a store whether it is blocked or can forward In addition this event does not count for specific threads correctly Implication If In...

Page 50: ... next VM entry instruction may fail to flush all TLB entries for the page Such entries may persist in the TLB until the next VM entry instruction Implication Accesses to the large page between INVLPG and the next VM entry instruction may incorrectly use translations that are inconsistent with the in memory page tables Workaround None Identified Status For the steppings affected see the Summary Tab...

Page 51: ...a load that crosses cache lines with data forwarded from a store and whose corresponding breakpoint enable flags are disabled DR7 G0 G3 and DR7 L0 L3 the DR6 B0 B3 flags may be incorrect Implication The debug exception DR6 B0 B3 flags may be incorrect for the load if the corresponding breakpoint enable flag in DR7 is disabled Workaround None identified Status For the steppings affected see the Sum...

Page 52: ...rkaround BIOS should zero the IA32_MC8_CTL2 MSR after a warm reset Status For the steppings affected see the Summary Tables of Changes AAO114 The TPM s Locality 1 Address Space Can Not be Opened Problem Due to this erratum writing to TXT CMD OPEN LOCALITY1 FED2_0380H does not open the Locality 1 address space to the TPM Trusted Platform Module Implication Software that uses the TPM s Locality 1 ad...

Page 53: ...accesses are wrapped around a 4 Gbyte boundary Status For the steppings affected see the Summary Tables of Changes AAO118 IOTLB Invalidations Not Completing on Intel VT d Engine for Integrated High Definition Audio Problem IOTLB invalidation in the Intel VT d engine for integrated High Definition Audio device may not complete and cause IVT field bit 63 of IOTLBINV register Offset 0x1208 in Memory ...

Page 54: ...54 Specification Update Workaround None identified Status For the steppings affected see the Summary Tables of Changes ...

Page 55: ...el 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming G...

Page 56: ...cture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Prog...

Page 57: ...chitectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation Note Documentation changes for Intel 64 and IA 32 Architecture Software Developer s Manual volumes 1 2A 2B 3A and 3B ...

Page 58: ...le_LFD_SVR Intel Xeon Processor 3400 Series ProductName_DT_LFD_NDA Lynnfield processor Desktop ProductName_SVR_LFD_NDA Intel Xeon Processor 3400 Series Lynnfield DateNDA September 2009 RevisionNumberNDA 001 Ref_Num_NDA_LFD CDI IBL 422224 Ref_Num_NDA_LFD_SVR CDI IBL 422225 DatePUB October 2009 RevisionNumberPUB 001 ReferenceNumberPUB TBD Other Variables Title Intel Core i7 Processor DocumentStatus ...

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Page 63: ...63 Specification Update Revision History 5 Preface 6 Summary Tables of Changes 8 Identification Information 16 Errata 19 Specification Changes 55 Specification Clarifications 56 Documentation Changes 57 ...

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