40
Specification Update
AAO66.
Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
Problem:
The performance monitor events DCACHE_CACHE_LD (Event 40H) and
DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1
cache. Due to this erratum, in addition to counting the completed loads and stores, the
counter will incorrectly count speculative loads and stores that were aborted prior to
completion.
Implication:
The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may
reflect a count higher than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO67.
Rapid Core C3/C6 Transitions May Cause Unpredictable System
Behavior
Problem:
Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions
in a system with Intel
®
Hyper-Threading Technology enabled may cause a machine
check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable
system behavior.
Implication:
This erratum may cause a machine check error, system hang or unpredictable system
behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO68.
Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
Problem:
The performance monitor event INSTR_RETIRED (Event C0H) should count the number
of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number
of load or store instructions retired. However, due to this erratum, they may
undercount.
Implication:
The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect
a count lower than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO69.
A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
Problem:
On processors supporting Intel
®
64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due
to this erratum, PS of such an entry is ignored and no page fault will occur due to its
being set.
Implication:
Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround:
Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
"1".
Status:
For the steppings affected, see the Summary Tables of Changes.
Summary of Contents for BV80605001914AG - Processor - 1 x Xeon X3430
Page 1: ...Reference Number 322373 009 Intel Xeon Processor 3400 Series Specification Update May 2010 ...
Page 4: ...Contents 4 Specification Update ...
Page 59: ...59 Specification Update October 2009 ...
Page 60: ...60 Specification Update March 2008 ...
Page 61: ...61 Specification Update October 2009 ...
