Intel BOXD915GVWBL - Desktop Board D915GVWBL, Manual, Page: 16 / 84

Intel Desktop Board D915GVWB Technical Product Specification
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Non-ECC DIMMs
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Serial Presence Detect
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DDR 400 MHz and DDR 333 MHz SDRAM DIMMs
Table 4 lists the supported system bus frequency and memory speed combinations.
Table 4. Supported System Bus Frequency and Memory Speed Combinations
To use this type of DIMM… The processor's system bus frequency must be…
DDR 400 800 MHz
DDR 333 (Note) 800 or 533 MHz
Note: When using an 800 MHz system bus frequency processor, DDR 333 memory is clocked at 320 MHz. This minimizes
system latencies to optimize system throughput.
NOTES
To be fully compliant with all applicable DDR SDRAM memory specifications, the board should be
populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This allows
the BIOS to read the SPD data and program the chipset to accurately configure memory settings
for optimum performance. If non-SPD memory is installed, the BIOS will attempt to correctly
configure the memory settings, but performance and reliability may be impacted or the DIMMs
may not function under the determined frequency.
Table 5 lists the supported DIMM configurations.
Table 5. Supported Memory Configurations
DIMM
Capacity
Configuration SDRAM
Density SDRAM Organization
Front-side/Back-side Number of SDRAM
Devices
128 MB SS 256 Mbit 16 M x 16/empty 4
256 MB SS 256 Mbit 32 M x 8/empty 8
256 MB SS 512 Mbit 32 M x 16/empty 4
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
512 MB SS 512 Mbit 64 M x 8/empty 8
512 MB SS 1 Gbit 64 M x 16/empty 4
1024 MB DS 512 Mbit 64 M x 8/64 M x 8 16
1024 MB SS 1 Gbit 128 M x 8/empty 8
2048 MB DS 1 Gbit 128 M x 8/128 M x 8 16
Note: In the second column, “DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers
to single-sided memory modules (containing one row of SDRAM).
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INTEGRATOR’S NOTE
It is possible to install four 2048 MB (2 GB) modules for a total of 8 GB of system memory,
however, only 4 GB of address space is available. Refer to Section 2.2.1, on page 39 for additional
information on available memory.