Intel Desktop Board DH61WW Technical Product Specification
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Table 38. Port 80h POST Codes
Port 80 Code
Progress Code Enumeration
ACPI S States
0x00,0x01,0x02,0x03,0x04,0x05
Entering S0, S2, S3, S4, or S5 state
0x10,0x20,0x30,0x40,0x50
Resuming from S2, S3, S4, S5
Security Phase (SEC)
0x08
Starting BIOS execution after CPU BIST
0x09
SPI prefetching and caching
0x0A
Load BSP microcode
0x0B
Load APs microcodes
0x0C
Platform program baseaddresses
0x0D
Wake Up All APs
0x0E Initialize
NEM
0x0F
Pass entry point of the PEI core
PEI before MRC
PEI Platform driver
0x11
Set bootmode, GPIO init
0x12
Early chipset register programming including graphics init
0x13
Basic PCH init, discrete device init (1394, SATA)
0x14 LAN
init
0x15
Exit early platform init driver
PEI SMBUS
0x16 SMBUSriver
init
0x17
Entry to SMBUS execute read/write
0x18
Exit SMBUS execute read/write
PEI CK505 Clock Programming
0x19
Entry to CK505 programming
0x1A
Exit CK505 programming
PEI Over-Clock Programming
0x1B
Entry to entry to PEI over-clock programming
0x1C
Exit PEI over-clock programming
Memory
0x21
MRC entry point
0x23
Reading SPD from memory DIMMs
0x24
Detecting presence of memory DIMMs
0x27 Configuring
memory
0x28 Testing
memory
0x29
Exit MRC driver
PEI after MRC
0x2A
Start to Program MTRR Settings
0x2B
Done Programming MTRR Settings
continued
