Intel ATX 3.0, Design Manual

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Electrical
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Table 4-9: Power Supply Timing
Parameter Description
Value
Legacy Timings
1
Required
Recommended
for ALPM
T0 AC power on time - <2s -
T1 Power-on time < 500 ms < 200 ms <150 ms
T2 Rise time - 0.2 – 20 ms -
T3 PWR_OK delay 100 ms 2 – 500 ms 100 ms 2 – 250 ms 100 ms 2 – 150 ms
T4 PWR_OK rise time - < 10 ms -
T5
AC loss to PWR_OK
hold-up time
3
- > 16 ms -
T6
PWR_OK inactive to
DC loss delay
- > 1 ms -
1. Value in the Legacy column list timings for power supplies designed before the
year 2020. In 2020, the T1 and T3 timings have moved from the Legacy timing to
the new Required column for all new power supply designs.
2. T3 minimum time faster than 100 ms is not recommended for previous generation
motherboards and systems. All design tolerances must be considered before
allowing T3 faster than 100 ms.
a.
A T3 time less than 100 ms may be designed based on system requirements
and a need to provide faster PSU and system turn on capability. However,
PSU and system designers are highly recommended to verify and ensure no
PSU and system compatibility problems exist, especially for previous
generation motherboards and systems.
3. T5 to be defined for both max/min load condition.
4. PSUs are recommended to label or indicate the timing value for system designer
and integrator reference for T1 and T3. This allows system designers to optimize
“turn on” time within the system.
4.3.1 PWR_OK – REQUIRED
PWR_OK is a “power good” signal. This signal shall be asserted high by the power
supply to indicate that the +12 VDC, +5 VDC, and +3.3 VDC outputs are within the
regulation thresholds listed in Table 4-2 and that sufficient mains energy is stored by
the converter to guarantee continuous power operation within the specification for at
least the duration specified in Section 4.2.9 . Conversely, PWR_OK should be de-
asserted to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output
voltages fall below its voltage threshold, or when mains power has been removed for
a time sufficiently long enough, such that power supply operation cannot be
guaranteed. The electrical and timing characteristics of the PWR_OK signal are given
in Table 4-10 .
PSU manufacturers are required to label or tag PSU DG revision or ATX spec
revision to show compliance and reflect the timing supported.