Schematic, Layout, and Routing Updates
R
Schematic, Layout, and Routing Updates
1.
Schematic Change to the 82845SDR MCH HSWING Circuit
Reference Appendix A, Customer Reference Board Schematics, of the Intel® Pentium® 4
Processor in 478-Pin Package and Intel® 845 Chipset Platform for SDR Design Guide, 298354-
002, dated January 2002. Sheet 11 of the “Intel® 845 SDR Schematics Rev 1.3” contains a circuit
at grid location C-7. This circuit has a VCCP input and an HSWING output. Capacitor C5D6 is
shown as a series capacitor between VCCP and the HSWING output. This circuit is not correct as
shown.
Capacitor C5D6 is a decoupling capacitor. It should connect the HSWING output of this circuit to
GND so that resistor R5D5 and capacitor C5D6 are in parallel.
Sheets
62,61,60,59,46,18,17,11,10,9,7,6,5
VCCP IN
R5D7
R5D5
C5D6
HSWING OUT
Sheet 9
Design Guide Update
9
