Intel 82547EI Design Manual Download Page 1

Page: 1 / 66

82562EZ(EX)/82547GI(EI) Dual
Footprint

Design Guide

Networking Silicon

317520-002

Revision 2.2

Summary of Contents for 82547EI

Page 1: ...82562EZ EX 82547GI EI Dual Footprint Design Guide Networking Silicon 317520 002 Revision 2 2...

Page 2: ...undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The product s described in this...

Page 3: ...new starting values for RBIAS100 and RBIAS10 New starting values are now 649 for RBIAS100 and 619 for RBIAS10 Updated reference schematics to reflect new Tx and Rx termination values new LAN disable c...

Page 4: ...iv 82562EZ EX 82547GI EI Dual Footprint Note This page is intentionally left blank...

Page 5: ...dules for 82562EZ EX PLC Device 14 3 2 4 Power Supplies for 82562EZ EX PLC Implementations 14 3 2 5 82562EZ EX Device Test Capability 14 3 3 Designing with the 82547GI EI Gigabit Ethernet Controller 1...

Page 6: ...l Layer Conformance Testing 30 4 5 Troubleshooting Common Physical Layout Issues 31 5 0 Design and Layout Checklists 33 6 0 Ball Number to Signal Mapping with Population Options 35 7 0 Dual Footprint...

Page 7: ...5 5 Crystal Parameters 7 6 82547GI EI Recommended Crystals 8 7 82562EZ EX Memory Layout 128 Byte EEPROM 13 8 82562EZ EX Memory Layout 512 Byte EEPROM 14 9 82562EZ EX Recommended Magnetics Modules 14 1...

Page 8: ...viii 82562EZ EX 82547GI EI Dual Footprint Design Guide Note This page intentionally left blank...

Page 9: ...nection speed and manageability As the requirements change footprint compatibility makes it possible to re focus the platform without the need to redesign a new a motherboard 1 1 Scope This applicatio...

Page 10: ...GI EI 82541ER EEPROM Map and Programming Information Intel Corporation ICH2 Integrated LAN Controller Function Disable and Power Control Intel Corporation PCI Bus Power Management Interface Specifica...

Page 11: ...I O Control Hub 5 ICH5 LCI is a point to point interface optimized to support one device Line termination mechanisms are not specified for the LCI Slew rate controlled output buffers achieve acceptab...

Page 12: ...abit Ethernet Controller and the MCH please refer to the Intel 865 Chipset design guide or the Intel 875 Chipset design guide 2 2 1 Generation Distribution of Reference Voltages The 11 bit CSA port on...

Page 13: ...greater than 1 inch place more than one 0 01 F capacitor near the reference voltage pin The trace length from the voltage divider circuit to the CI_REF pins must be no longer than 3 5 inches Both the...

Page 14: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 6 Note This page intentionally left blank...

Page 15: ...of frequency control components due to their low cost and ease of implementation They are available from numerous vendors in many package types and with various specification options All crystals use...

Page 16: ...Ethernet physical layer device is dictated by the IEEE 802 3 specification as 50 parts per million ppm This measurement is referenced to a standard temperature of 25 C Note Intel recommends a frequen...

Page 17: ...parallel LC circuit Figure 4 Crystal Circuit 3 1 1 6 Load Capacitance The formula for crystal load capacitance is as follows where C1 C2 22 pF as suggested in most Intel reference designs and Cstray...

Page 18: ...Mounted Technology SMT crystal is less than its through hole counterpart because surface mount crystals are typically made from narrow rectangular AT strips rather than circular AT quartz blanks Some...

Page 19: ...ise within 50 ppm Intel recommends customers to use a transmitter reference frequency that is accurate to within 30 ppm to account for variations in crystal accuracy due to crystal manufacturing toler...

Page 20: ...sample as well as meeting the published specifications 3 Perform physical layer conformance testing and EMC FCC and EN testing in real systems Vary temperature and voltage while performing system leve...

Page 21: ...EEPROM the 82562EZ EX may or may not support legacy manageability Table 7 and Table 8 list the EEPROM map for the 82562EZ EX PLC device For details on the EEPROM refer to the appropriate I O Control H...

Page 22: ...bility The device contains an XOR test tree mechanism for simple board tests Details of the XOR tree operation are contained in the 82562ET LAN on Motherboard Design Guide 3 3 Designing with the 82547...

Page 23: ...guration for the 82562EZ EX Platform LAN Connect device be sure the AND gate U1 is populated Depopulate the 0 resistor R2 Figure 6 82547GI EI LAN Disable Circuitry 3 3 2 Serial EEPROM for 82547GI EI C...

Page 24: ...nnings and ends of read and write cycles The extra pulses may violate the timing specifications of some EEPROM devices In selecting a serial EEPROM choose a device that specifies don t care shift cloc...

Page 25: ...upplies for the 82547GI EI Device The 82547GI EI controller requires three power supplies The 1 2 V supply must provide approximately 550 mA current The 1 8 V supply must provide approximately 230 mA...

Page 26: ...as possible 3 3 7 82547GI EI Controller Power Management and Wake Up The 82547GI EI Gigabit Ethernet Controller supports low power operation as defined in the PCI Bus Power Management Specification Th...

Page 27: ...to pads accessible by your test equipment Be sure to connect the TRST input to ground through a pull down resistor approximately 1k value so that the test capability cannot be invoked by mistake A BS...

Page 28: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 20 Note This page intentionally left blank...

Page 29: ...bit operation is very similar to designing for 10 and 100 Mbps For the 82547GI EI Gigabit Ethernet controller system level tests should be performed at all three speeds 4 1 1 Guidelines for Component...

Page 30: ...rnet magnetics module to prevent interference Traces should be referenced to a continuous low impedance plane Place the crystal and load capacitors on the printed circuit boards as close to the Ethern...

Page 31: ...s are much more likely to have degraded receive Bit Error Rate BER performance IEEE PHY conformance failures and or excessive Electromagnetic Interference EMI radiation Do not route the transmit diffe...

Page 32: ...the fiberglass layer is eight mils 0 2 mm thick with a dielectric constant ER of 4 7 the calculated single ended impedance would be approximately 61 and the calculated differential impedance would be...

Page 33: ...lihood of crosstalk The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software 4 1 9 Signal Isolation To maintain best signal integrity keep d...

Page 34: ...h it Split Ground Planes for Magnetics Modules 4 1 11 Traces for Decoupling Capacitors Traces between decoupling and I O filter capacitors should be as short and wide as practical Long and thin traces...

Page 35: ...ermine which value s provide best EMI performance Figure 8 Ideal Ground Split Implementation The table below gives some starting values for these capacitors The placement of C1 C6 may also be differen...

Page 36: ...chassis ground signal ground or a termination plane Care must be taken when using various grounding methods to insure that emission requirements are met In the Bob Smith termination method a floating...

Page 37: ...he positive peak Ideally a typical PCB output amplitude should be within 975 mVpk to 1025 mVpk for the negative peak and 975 mVpk to 1025 mVpk for the positive peak For 10Base T designs the IEEE speci...

Page 38: ...ikely to be integral to a magnetics module take care with care to route the LED traces away from potential sources of EMI noise In some cases it may be desirable to attach filter capacitors 4 4 Physic...

Page 39: ...l traces After exiting the Ethernet silicon the trace pairs should be kept 0 3 inches or more away from the other trace pairs The only possible exceptions are in the vicinities where the traces enter...

Page 40: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 32 Note This page intentionally left blank...

Page 41: ...EZ EX 82547GI EI Dual Footprint Design Guide 33 5 0 Design and Layout Checklists The Design and Layout checklists are in Portable Data Format PDF and available to aid designers via http developer inte...

Page 42: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 34 Note This page intentionally left blank...

Page 43: ...r design tools Table 14 Ball Number to Signal Mapping Sheet 1 of 7 Ball Ref 82562EZ EX Pin Name 82547GI EI Pin Name Signal Name Difference 82562EZ EX Connection Pop Option Required Comment A1 NC NC A2...

Page 44: ...C4 NC EEMODE X C5 NC NC X C6 NC NC X C7 NC NC X C8 NC NC X C9 NC SMBDATA X C10 VSS VSS X C11 ACTLED LED ACTIVITY X X X Same signal different name C12 VSS ANALOG_VSS X C13 TDP MDI 0 X X X Connected to...

Page 45: ...o VSS E5 VSS VSS X E6 VSS VSS X E7 VSS VSS X E8 VSS VSS X E9 VSS VSS X E10 VSS VSS X X X Connected to VSS E11 VCCT ANALOG_1 2V X X X 3 3 V 1 2 V Plane E12 VCCT ANALOG_1 2V X X X 3 3 V 1 2 V Plane E13...

Page 46: ...1 2 V Plane G14 VSS ANALOG_VSS X H1 NC CI 10 X H2 NC CSA_VSS X H3 NC CI 8 X H4 NC CSA_1 2V X H5 VCCR 1 2 V X X X 3 3 V 1 2 V Plane H6 VCC 1 2 V X X X 3 3 V 1 2 V Plane H7 VCC 1 2 V X X X 3 3 V 1 2 V P...

Page 47: ...Connected to 3 3 V K5 VCC 1 2 V X X X 3 3 V 1 2 V Plane K6 VCC 1 2 V X X X 3 3 V 1 2 V Plane K7 VCC 1 2 V X X X 3 3 V 1 2 V Plane K8 VCC 1 2 V X X X 3 3 V 1 2 V Plane K9 VCC 1 2 V X X X 3 3 V 1 2 V Pl...

Page 48: ...TAG Connect M1 NC CI 6 X M2 NC CI 5 X M3 NC CSA_VSS X M4 NC CSA_1 2V X M5 NC 1 2 V X M6 VSS VSS X M7 NC NC X M8 NC NC X M9 NC FLSH_CE X M10 NC EESK X M11 NC FLSH_SI X M12 JRXD 2 SDP 3 X X X 82562EZ IC...

Page 49: ...0 X X X 82562EZ ICH LAN Connect 82547GI EI No Connect P1 NC NC P2 VCC 3 3 V X P3 NC CI_SWING X P4 NC NC X P5 NC NC X P6 NC NC X P7 NC EECS X P8 VSS VSS X P9 NC FLSH_SO LAN_DISABLE X P10 NC EEDI X P11...

Page 50: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 42 Note This page is intentionally left blank...

Page 51: ...rint Design Guide 43 7 0 Dual Footprint Reference Schematic The following pages illustrate a dual purpose 10 100 and 10 100 1000 design using the 82562EZ EX Platform LAN Connect device and the 82547GI...

Page 52: ...W Q H Q R S P R F V L K W O O D W V Q Y H 5 1 6 1 5 5 1 3 H J D 3 H O W L 7 V H F D I U H W Q 7 P R U S K V D O W H Q U H K W V X 0 6 V H F D I U H W Q W F H Q Q R 1 G Q D P R U S W H Q U H K W V Q L...

Page 53: ...L 0 F L J R 7 R W H W X R 5 H F D I U H W Q W F H Q Q R 1 H W X R 5 U H O O R U W Q R F R W H F L Y H G P R U S H Q R O Q R H W D O X S R 3 U R W Q H P H J D Q D P Q R Q U R I H U L Z R U F L 0 W U R...

Page 54: ...15mm BGA 1mm Pitch Place these capacitors close to their respective pins of the 82547GI EI Place these capacitors close to the divider network Internal PHY clock test point IEEE conformance testing P...

Page 55: ...DFH ZLWK QWHJUDGHG 0DJQHWLFV 5 RU WKH GLIIHUHQWLDO SDLUV DUH WHUPLQDWHG XVLQJ RKP UHVLVWRUV 7 3 5 1 7 1 5 3 2 25 63 7KHVH WKUHH FDSDFLWRUV DFURVV WKH 66 6B 1 WR 1 VSOLW DUH ORFDWHG DERYH WKH PDJQHWLFV...

Page 56: ...er the LAN power rails are stable Note For the 82562EZ EX the BIOS must delay driving LAN_RST for 20ms after resetting the ICH Use the AND gate shown if this timing is not already accounted for in you...

Page 57: ...6 8 Q R L V U H Y J L 0 D H V X W R Q R G V Q J L V H G U R V U R W L F D S D F S D W U H W Q H F V D K W D K W R V O D U R W F H Q Q R V Q L 3 V W U R S 6 8 V H G X O F Q L O R E P V V L K W Q R Q Z...

Page 58: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 50 Note This page intentionally left blank...

Page 59: ...should be used to measure the transmitter reference frequency or transmitter reference clock If the transmitter reference frequency is more than 20 ppm below the target frequency then the values for...

Page 60: ...ng of the transmitter reference clock The buffered 125 MHz clock will be a 5X multiple of the crystal circuit s reference frequency Figure 11 Different LAN devices may require different register setti...

Page 61: ...n Appendix B GigConf exe Register Settings for 82547GI EI Devices 5 Determine the center reference frequency as accurately as possible This can be done by taking 30 to 50 different readings using the...

Page 62: ...frequency then the values for C1 and C2 are too small and they should be increased When tests are performed across temperature it may be acceptable for the center frequency deviation to be a little gr...

Page 63: ...r model of high resolution digital counter make sure it can display 25 0000 MHz with at least four decimal places frequency resolution 4 Ensure the LAN circuits are powered 5 Determine the center refe...

Page 64: ...low the target frequency then the values for C1 and C2 are too big and they should be decreased When tests are performed across temperature it may be acceptable for the center frequency deviation to b...

Page 65: ...et Address field on the right side of the screen use the right arrow key 13 Press Enter to select the highlighted value and then use Backspace to clear out the current value 14 Type 4011 for the value...

Page 66: ...82562EZ EX 82547GI EI Dual Footprint Design Guide 58 Note This page intentionally left blank...

Search results

Summary of Contents for 82547EI

Reviews:

Related manuals for 82547EI

Brands by name

Popular brands

Intel 82547EI, Design Manual

Search results

Summary of Contents for 82547EI

Reviews:

Related manuals for 82547EI

Brands by name

Popular brands