Intel
®
81341 and 81342—Timers
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
816
Order Number: 315037-002US
12.4.2.4 Bit 3 — Timer Register Privileged Read/Write Control (TMRx.pri)
The TMRx.pri bit enables or disables user mode writes to the timer registers (TMRx,
TCRx, TRRx). Privileged mode writes are allowed regardless of this bit’s condition.
Software can read these registers from either mode. Note that TMR1.pri also controls
“Watch Dog Timer Control Register — WDTCR” on page 819
and the
“Watch Dog Timer Setup Register — WDTSR” on page 819
When:
The processor clears TMRx.pri upon hardware or software reset.
12.4.2.5 Bits 4, 5 — Timer Input Clock Select (TMRx.csel1:0)
User software programs the TMRx.csel bits to select the Timer Clock (TCLOCK)
frequency. See
. As shown in
, the internal bus clock is an input to
the timer clock unit. These bits allow the application to specify whether TCLOCK runs at
or slower than the internal bus clock frequency.
The processor clears these bits upon hardware or software reset
(TCLOCK = Core Clock).
TMRx.pri = 1
The timer ignores the user mode write to the timer registers;
however, writes from the privileged modes are allowed.
TMRx.pri = 0
The timer registers can be written from either the user mode or
the privileged modes.
Table 497. Timer Input Clock (TCLOCK) Frequency Selection
Bit 5
TMRx.csel1
Bit 4
TMRx.csel0
Timer Clock (TCLOCK)
0
0
Timer Clock = internal bus clock
0
1
Timer Clock = internal bus clock / 4
1
0
Timer Clock = internal bus clock / 8
1
1
Timer Clock = internal bus clock / 16
