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Intel

81341 and 81342 I/O Processors

December 2007

Developer’s Manual

Order Number: 315037-002US

717

Peripheral Bus Interface Unit—Intel

81341 and 81342

9.2.6.2

Flash Write Cycle

Address-to-data and recovery wait states for reads and writes are identical and

programmed in PBBAR0 and PBBAR1. Refer to

Table 432

for the programmable

address-to data wait states. However, Any write transactions issued to a Peripheral

address space window must always represent a single peripheral bus data cycle (

strb,

strh

) depending on the bus width selected in PBBAR0 — PBBAR1.

The PBI supports multi-byte write requests from the internal bus agents. Multi-byte

read and write requests are supported differently by the PBI. Write requests are limited

to a maximum of four bytes only and must not span a DWORD boundary. For a write

request with an address and byte-count combination that spans a DWORD boundary,

the PBI signals an address error and set bit 0 of the

“PBI Status Register — PBISR” on

page 719

. Unlike multi-byte read requests, the PBI supports multi-byte write requests

by breaking the writes on the PBI bus into multiple single data write transactions. The

number of single data write transactions initiated on the PBI bus are dependent to the

PBI bus width. For example, an aligned DWORD write on an 8-bit PBI bus turns into

four single 8-bit write transactions on the PBI bus, and an aligned DWORD write

request on a 16-bit PBI bus turns into two single 16-bit write transactions on the PBI

bus.

Figure 111

shows the only type of write transaction supported by the PBI bus. For

example, each write transaction ends after one data transfer to a single address

location regardless of bus width.

Figure 111

illustrates a write cycle example for a 120 ns Flash device. Both 8- and 16-

bit wide bus timings are identical.

Figure 111. 120 ns Flash Single Write Cycle

Notes:

The PBI bus does not burst write transactions. A multi-byte write request made to the PBI is translated

into multiple single data write transactions on the PBI bus. And the number of single data write

transactions initiated on the PBI bus are dependent to the PBI bus width.

A[24:03]

A[02:00]

Ta2

Tw1

Tw8

Td2

Tr1

Tr4

POE #

PWE#

PCEx#

D[15:00]

D_out

Ti/Ta

Ta1

Td 1

B6271-01

Summary of Contents for 81341

Page 1: ...Order Number 315037 002US Intel 81341 and 81342 I O Processors Developer s Manual December 2007...

Page 2: ...errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an or...

Page 3: ...r Communication 52 1 5 16 Inter Processor Messaging Unit 52 1 5 17 Timers 52 1 5 18 GPIO 52 1 6 Terminology and Conventions 53 1 6 1 Representing Numbers 53 1 6 2 Fields 53 1 6 3 Specifying Bit and Si...

Page 4: ...2 2 7 3 1 Outbound Read Request Uncorrectable Data Errors 103 2 7 3 1 1 Immediate Data Transfer 103 2 7 3 1 2 Split Response Termination 104 2 7 3 2 Outbound Write Request Uncorrectable Data Errors 10...

Page 5: ...2 7 9 1 2 Inbound Read Request 121 2 7 9 2 Target Abort on the Internal Bus 122 2 7 9 2 1 Conventional Mode 122 2 7 9 2 2 PCI X Mode 122 2 7 9 3 Parity Error on the Internal Bus 123 2 7 9 3 1 Convent...

Page 6: ...34Inbound ATU Limit Register 2 IALR2 178 2 13 35Inbound ATU Translate Value Register 2 IATVR2 179 2 13 36Inbound ATU Upper Translate Value Register 2 IAUTVR2 179 2 13 37Expansion ROM Limit Register E...

Page 7: ...dress Register PCIEAR 226 2 13 84PCI Interface Error Upper Address Register PCIEUAR 227 2 13 85PCI Interface Error Context Address Register PCIECAR 228 2 13 86Internal Arbiter Control Register IACR 22...

Page 8: ...ole Based Error Reporting 275 3 9 1 2 Malformed Packets 276 3 9 1 3 ECRC Check Failed 276 3 9 1 4 Unsupported Request 277 3 9 1 5 Completer Abort 277 3 9 1 6 Unexpected Completions 277 3 9 1 7 Poisone...

Page 9: ...R2 327 3 16 36Inbound ATU Upper Translate Value Register 2 IAUTVR2 328 3 16 37Expansion ROM Limit Register ERLR 328 3 16 38Expansion ROM Translate Value Register ERTVR 329 3 16 39Expansion ROM Upper T...

Page 10: ...apability Register PWRBGT_CAP 374 3 16 91Power Budgeting Information Registers 0 23 PWRBGT_INFO 0 23 375 3 16 92Outbound I O Base Address Register OIOBAR 376 3 16 93Outbound I O Window Translate Value...

Page 11: ...ed Versus Edge Triggered Interrupts 424 4 9 Register Definitions 425 4 9 1 Inbound Message Register IMRx 427 4 9 2 Outbound Message Register OMRx 427 4 9 3 Inbound Doorbell Register IDR 428 4 9 4 Inbo...

Page 12: ...x 462 4 10 Power Default Status 462 5 0 Application DMA Unit 463 5 1 Overview 463 5 2 Theory of Operation 464 5 3 ADMA Descriptors 466 5 3 1 Basic Chain Descriptor Format 467 5 3 2 Full Chain Descript...

Page 13: ...r x CARMDQx 529 5 16 8 ADMA Byte Count Register x ABCRx 530 5 16 9 Destination Lower Address P_Destination Lower Address Register x DLADRx 531 5 16 10Destination Upper Address PQ_Destination Upper Add...

Page 14: ...l Bus Port Address Decode 567 7 3 1 2 4 South Internal Bus Port Address Decode 567 7 3 1 2 5 Application DMA Port Address Decode 567 7 3 1 3 Memory Transaction Queues 568 7 3 1 3 1 North Internal Bus...

Page 15: ...bit Region Size Register S32SR 637 7 8 9 DDR ECC Control Register DECCR 638 7 8 10 DDR ECC Log Registers DELOG0 DELOG1 639 7 8 11 DDR ECC Address Registers DEAR0 DEAR1 641 7 8 12 DDR ECC Context Addre...

Page 16: ...8 3 1 3 1 North Internal Bus Port Transaction Queue NIBPTQ 678 8 3 1 4 Configuration Registers 678 8 3 1 5 SRAM Control Block 678 8 3 1 5 1 SRAM State Machine and Pipeline Queues 678 8 3 1 5 2 Error C...

Page 17: ...9 3 6 PBI Base Address Register 1 PBBAR1 723 9 3 7 PBI Limit Register 1 PBLR1 724 9 3 8 PBI Drive Strength Control Register PBDSCR 725 9 3 9 Processor Frequency Register PFR 726 9 3 10 External Strap...

Page 18: ...ize Register INTSIZE 759 11 7 3 IRQ Interrupt Vector Register IINTVEC 760 11 7 4 FIQ Interrupt Vector Register FINTVEC 761 11 7 5 Inter Processor Interrupt Pending Register IPIPNDR 762 11 7 6 Interrup...

Page 19: ...iew 821 13 2 Door Bell Registers 822 13 2 1 Door Bell Register Operation 823 13 3 Circular Queues 824 13 3 1 Circular Queue Operation 825 13 3 1 1 Send Queue Management 827 13 3 1 2 Receive Queue Mana...

Page 20: ...6 37IMU Test and Set Registers IMUTSR 0 511 858 13 6 37 1Endian Mode Support 859 14 0 SMBus Interface Unit 861 14 1 Overview 861 14 2 SMBus Interface 861 14 3 System Management Bus Interface 862 14 3...

Page 21: ...904 15 4 10Divisor Latch Registers 905 15 4 11UART x FIFO Occupancy Register 906 15 4 12UART x Auto Baud Control Register 907 15 4 13UART x Auto Baud Count Register 908 16 0 I2C Bus Interface Units 9...

Page 22: ...18 3 Definitions 949 18 4 Data Collection 950 18 4 1 Time Based Sampling 950 18 4 2 Hardware Event Based Control 952 18 4 3 Incrementing By More Than 1 954 18 4 4 Queue Analysis 955 18 5 Non Register...

Page 23: ...Function Select 1001 19 5 Reset Strapping Options 1002 20 0 Test Logic Unit and Testability 1005 20 1 Overview 1005 20 2 IEEE 1149 1 Standard Test Access Port TAP 1006 20 2 1 TAP Pin Description 1007...

Page 24: ...1022 21 6 1 Internal Units 1025 21 6 1 1 Application DMA 0 2 1025 21 6 1 2 Inter Processor Messaging Unit 1027 21 6 1 3 SRAM Memory Controller 1029 21 6 1 4 Peripheral Bus Interface Unit 1030 21 6 1 5...

Page 25: ...rmat VPD Capability 147 23 ATU Block Diagram 236 24 ATU Queue Architecture Block Diagram 237 25 Inbound Address Detection 243 26 Inbound Translation Example 244 27 4 Gbyte Section 0 of the Internal Bu...

Page 26: ...am 565 79 Intel 81341 and 81342 I O Processors Dual Bank DDR SDRAM Memory Subsystem 574 80 DDR SDRAM 64 bit Memory Address Map 580 81 DDR SDRAM 64 bit Physical Map 580 82 Secondary DDR SDRAM Window Me...

Page 27: ...ation Read Protocol SMBus Word Write Word Read PEC Disabled 871 133 DWORD Memory Read Protocol SMBus Word Write Word Byte Read PEC Enabled 871 134 DWORD Memory Read Protocol SMBus Word Write Byte Read...

Page 28: ...Histogram Example 959 165 Processing of HOQ Histogram Example 960 166 Output from HOQ Histogram Example 960 167 Indicator Tree 962 168 Intel 81341 and 81342 I O Processors Clocking Regions Diagram 98...

Page 29: ...sets 151 25 ATU Vendor ID Register ATUVID 152 26 ATU Device ID Register ATUDID 152 27 ATU Command Register ATUCMD 153 28 ATU Status Register ATUSR 154 29 ATU Revision ID Register ATURID 156 30 ATU Cla...

Page 30: ...CCCSR 200 81 ECC First Address Register ECCFAR 203 82 ECC Second Address Register ECCSAR 204 83 ECC Attribute Register ECCAR 205 84 HS_CAPID Hot Swap Cap ID 205 85 HS_NXTP Next Item Pointer 206 86 HS_...

Page 31: ...ion 272 130 Advisory Error Cases 275 131 PCI Express Error Summary 280 133 Internal Bus Error Summary 282 132 Root Complex Error Summary 282 134 ATU Internal Bus Memory Mapped Register Range Offsets 2...

Page 32: ...wer Management Control Status Register APMCSR 343 188 Scratch Pad Register ATUSPR 344 189 PCI Express Capability Identifier Register PCIE_CAPID 344 190 PCI Express Next Item Pointer Register PCIE_NXTP...

Page 33: ...387 238 Outbound Configuration Cycle Function Number OCCFN 388 239 Inbound Vendor Defined Message Header Register0 IVMHR0 389 240 Inbound Vendor Defined Message Header Register 1 IVMHR1 390 241 Inboun...

Page 34: ...xt_Ptr 451 296 Message Control Register Message_Control 452 297 Message Address Register Message_Address 453 298 Message Upper Address Register Message_Upper_Address 454 299 Message Data Register Mess...

Page 35: ...DDR2 SDRAM Address Translation for 512 Mbit x8 and 1 Gbit x8 Devices SDCR0 6 cleared 575 349 DDR2 SDRAM Address Translation for 2 Gbit x16 Device SDCR0 6 set 575 350 DDR2 SDRAM Address Translation for...

Page 36: ...al Override Values Register DQPDSR 656 401 MA Pad Drive Strength Manual Override Values Register ADPDSR 657 402 MCLK Pad Drive Strength Manual Override Values Register MPDSR 658 403 CKE CS Pad Drive S...

Page 37: ...troller Co Processor Register Addresses 756 458 Interrupt Base Register INTBASE 758 459 Interrupt Size Register INTSIZE 759 460 IRQ Interrupt Vector Register IINTVEC 760 461 FIQ Interrupt Vector Regis...

Page 38: ...Lower Base Address Register 0 SQLBAR0 838 515 Send Queue Upper Base Address Register 0 SQUBAR0 838 516 Receive Queue Put Get Pointer Register 0 RQPG0 839 517 Receive Queue Put Get Pointer Register 0...

Page 39: ...ceive Buffer Register UxRBR 890 565 UART x Transmit Holding Register UxTHR 890 566 UART x Interrupt Enable Register UxIER 891 567 UART x Interrupt Identification Register UxIIR 892 568 Interrupt Ident...

Page 40: ...Summary 977 618 DDR SDRAM Memory Controller Events 978 619 PCI Interface Events 981 620 PCI Express Interface Summary 982 621 North Internal Bus Source Select Summary 983 622 North Internal Bus Initia...

Page 41: ...37 661 Messaging Unit Offset 1038 662 Messaging Unit 1038 663 PMON Unit Base Address Offset 1040 664 PMON Unit 1040 665 PCI Function MMR Locations 1041 666 81341 and 81342 ATUX Configuration Space Bas...

Page 42: ...d 81342 I O Processors Developer s Manual December 2007 42 Order Number 315037 002US Revision History Date Revision Description December 2007 002 Revised Chapter 7 0 DDR SDRAM Memory Controller for 4G...

Page 43: ...ent This document describes the product specific features of the 81341 and 81342 Each chapter describes a different feature and starts with an overview followed by the theory of operation The reader s...

Page 44: ...r Performance Monitor Unit PMON Two Programmable Timers on the Intel XScale processor co processor bus Watchdog Timer on the Intel XScale processor co processor bus Three I2C Bus Interface Units Two S...

Page 45: ...am PCI X or PCI E Intel 81341 I O Processor 16 Bit I F I2C Bus 72 Bit I F Serial Bus Bridge Multi Port DDR II SDRAM Memory Controller Three Application DMA Channels Host Interface ATU Multi Port SRAM...

Page 46: ...ximum frequency of 1 5 GHz The instruction cache is 32 Kbytes in size and is 32 way set associative Also the core processor includes a data cache that is 32 Kbytes and is 32 way set associative and a...

Page 47: ...d SRAM Memory Controller Performance Monitor PMON Two Programmable Timers on the Intel XScale processor co processor bus Watchdog Timer on the Intel XScale processor co processor bus Three I2C Bus Int...

Page 48: ...72 Bit I F Serial Bus Bridge Multi Port DDR II SDRAM Memory Controller Three Application DMA Channels Host Interface ATU Multi Port SRAM Memory Controller Two UARTs Three I 2 C Bus Interface APB PBI...

Page 49: ...ssor Either interface on 81341 and 81342 is setup as a single function PCI device The upstream PCI interface is selected using an external strap The Address Translation Unit ATU and the Messaging Unit...

Page 50: ...is programmable through the Intel XScale processor and the host processor Each Application DMA channel can also be programmed to operate as an XOR Engine that provides low latency high throughput data...

Page 51: ...cts and support for error correction codes ECC The DDR Memory Controller is multi ported with the following interfaces south internal bus DMA controller north internal bus The memory controller interf...

Page 52: ...t sources both external and internal of sources of 81341 and 81342 to the Intel XScale processor processor The ICU supports high performance interrupt processing with direct interrupt service routine...

Page 53: ...ue Writes to read only fields are treated as no op operations and does not change the current value nor result in an error condition A read clear field can also be read to return the current value A w...

Page 54: ...of using the symbol at the end of a signal name to indicate that the signal s active state occurs when it is at a low voltage The absence of the symbol indicates that the signal s active state occurs...

Page 55: ...s Addresses and initiates the data transfer on the 81341 and 81342 internal bus During outbound transactions the ATU converts internal bus addresses to PCI addresses and initiates the data transfer on...

Page 56: ...evision 2 3 Hot Swap capability as defined by the Compact PCI Hot Swap Specification Revision 2 1 and PCI X capability as defined by PCI X Protocol Addendum to the PCI Local Bus Specification Revision...

Page 57: ...tel 81341 and 81342 Figure 4 ATU Queue Architecture Block Diagram P C I B u s I n t e r n a l B u s I n t e r f a c e P C I B u s I n t e r f a c e ADDRESS TRANSLATION UNIT I n t e r n a l B u s OWQ 4...

Page 58: ...nds supported for both inbound and outbound ATU transactions The type of operation seen by the ATU on inbound transactions is determined by the PCI master who initiates the transaction Claiming an inb...

Page 59: ...terrupt Acknowledge Interrupt Acknowledge No No Reserved 0001 Special Cycle Special Cycle No No Reserved 0010 I O Read I O Read No Yes Reserved 0011 I O Write I O Write No Yes Reserved 0100 Reserved R...

Page 60: ...ads are performed as split transactions Inbound memory write transactions have their addresses entered into the inbound write address queue IWADQ and data entered into the inbound write data queue IWQ...

Page 61: ...U Translate Value Register 0 Inbound ATU Upper Translate Value Register 0 The ATU uses the following registers in inbound address window 1 translation Inbound ATU Base Address Register 1 Inbound ATU L...

Page 62: ...se of DACs is first bitwise ANDed with the bitwise inverse of the limit register This result is bitwise ORed with the ATU Translate Value which is then ORed with the 4 bit ATU Upper Translate Value le...

Page 63: ...Mbyte limit value Inbound Window Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH 8 Mbytes PCI_Address Value_Register B100 0000H Internal_Bus Address PCI Address Space I O Processor Loc...

Page 64: ...rror is detected the uncorrectable attribute error mechanism described in Section 2 7 1 is used When an uncorrectable data error is detected while accepting data the slave interface sets the appropria...

Page 65: ...R may be asserted on the PCI interface The ATU initiator interface attempts a 128 bit wide transfer on the internal bus When the target that claims the request does not support 128 bit wide transfers...

Page 66: ...eturn the data to the master on the PCI bus When there is a match and the data is not available a Retry is signaled with no other action taken When there is not a match and when the ITQ has less than...

Page 67: ...s is target aborted either a target abort or a disconnect with data is signaled to the initiator This is based on the ATU ECC Target Abort Enable bit bit 0 of the ATUIMR for ATU When set a target abor...

Page 68: ...r interface performs an initiator completion in this case Also the completer reacquires the internal bus to deliver the remaining read data byte count to the ATU When operating in the conventional PCI...

Page 69: ...P_IDSEL active where P_AD 1 0 are not 002 e g Type 1 commands During the configuration access address phase the PCI address is divided into a number of fields to determine the actual configuration reg...

Page 70: ...split write in PCI X mode request cycle is latched into IDWQ and forwarded to the internal bus interface Once transaction ordering and priority have been satisfied the internal bus master interface re...

Page 71: ...nal PCI mode The timer starts counting when the delayed request becomes a delayed completion by completing on the internal bus and all passing rules are satisfied When the originating master on the PC...

Page 72: ...as split read operations Outbound transactions use a separate set of queues from inbound transactions Outbound write operations have their address entered into the outbound write address queue OWADQ a...

Page 73: ...ATU Configuration Register Outbound Enable bit as well as the Bus Master Enable bit in each function When the Outbound Enable bit is deasserted the internal bus outbound transaction master abort are...

Page 74: ...2 internal bus address space this removes the need for separate limit registers Figure 8 on page 74 illustrates the five outbound address translation windows Figure 8 Outbound Address Translation Wind...

Page 75: ...Internal Bus to PCI Command Translation for Memory Windows Internal Bus Command Conventional PCI Command PCI X Command Writea a The internal bus request does not cross a QWORD address boundary Memory...

Page 76: ...ry transactions the internal bus address is bitwise ANDed with the inverse of 4 Gbytes which clears the upper 4 bits of the 36 bit address The result is bitwise ORed with the outbound upper window val...

Page 77: ...target interface stores write data into the OWQ until the internal bus transaction completes or the reaches a buffer boundary The initiator of the transaction is disconnected at an ADB when the transa...

Page 78: ...ed the PCI interface transfers data from the OWQ to the PCI bus until one of the following is true The PCI target signals a Retry or Single Data Phase Disconnect The ATU PCI initiator attempts to reac...

Page 79: ...a split completion transaction to return data to the internal bus requester When operating in the PCI X mode ATU may receive a split completion error message when attempting to read data on the PCI bu...

Page 80: ...s 32 bit only Note the programming model uses the register interface for outbound configuration cycles from a hardware standpoint the address is entered into OTQ reads or OWADQ writes configuration wr...

Page 81: ...to set bits 27 24 properly 2 2 5 3 Outbound Configuration Cycle Error Conditions Master aborts during outbound configuration reads result in ATU aborting the read completion the on internal bus Targe...

Page 82: ...ber 315037 002US 2 2 6 Internal Bus Operation Complete internal bus operation of the 81341 and 81342 is defined in Chapter 6 0 System Controller SC and Internal Bus Bridge The ATU acts as both interna...

Page 83: ...ng MSI X 2 3 1 Inbound Byte Swapping When enabled the swapping occurs as described in Figure 9 Inbound Byte Swapping for 32 bit PCI on page 83 and Figure 10 Inbound Byte Swapping for 64 bit PCI on pag...

Page 84: ...Note The byte swapping capability of the ADMA unit should be used to swap bytes within each DWORD for PCI to Memory Read Write DMA transfers Figure 11 Outbound Byte Swapping for Transaction with Byte...

Page 85: ...stem host that the configuration of the system has changed The system host then performs any necessary maintenance such as installing or quiesing a device driver HS_LSTAT 1 I Compact PCI Hot Swap Latc...

Page 86: ...pins allow the 81341 and 81342 to determine the cPCI backplane operating frequency without needing to see a PCI X initialization pattern These pins are only valid when HS_SM is sampled as 0b during P...

Page 87: ...access by the assertion of ACK64 in response to a 64 bit request The Expansion ROM unit uses the ATU inbound transaction queue and the inbound read data queue When operating in the conventional PCI mo...

Page 88: ...en operating in the conventional PCI mode transactions The following rules apply to the PCI bus interface and govern the acceptance of data into IWQ and address into the tail of the IWADQ A memory wri...

Page 89: ...est cycle in both command and address Any data left in an IRQ after the delivery of a completion cycle on PCI is flushed This is possible since all internal bus memory is considered prefetchable with...

Page 90: ...s When operating in the PCI X mode a write completion message is generated by the ATU to indicate the successful execution of the configuration write transaction The IDWQ can only hold 32 bits of data...

Page 91: ...Read data is fetched and returned to the requester on the internal bus 2 6 2 1 Relaxed Ordering and No Snoop Outbound Request Attributes In PCI X mode the ATU may set the Relaxed Ordering RO bit 29 of...

Page 92: ...y strong ordering between outbound memory posted write requests and outbound non posted write requests are not maintained as indicated in Table 12 on page 93 For best performance the user should desig...

Page 93: ...Outbound Read Request SRR The address command of a split read cycle initiated on the internal bus The read data is returned in the Outbound Read Completion cycle Inbound Read Completion DRC PCI mode...

Page 94: ...ete on the internal bus before Transaction B since an outbound read completion can not pass an inbound write Also Transaction A must complete before Transaction C since an inbound write can not pass a...

Page 95: ...Is there an Inbound Write Request with an earlier time stamp Yes Do Not Assign Token Allow previous Transaction to Complete No Assign Token Inbound Read Request in ITQ Is there an Inbound Write with a...

Page 96: ...mpletion in IRQ Is there an Outbound Posted Write with an earlier time stamp Yes Do Not Assign Token Allow previous Transaction to Complete No Assign Token Is there an Inbound Read Completion with an...

Page 97: ...the internal bus interface the same data issues on the PCI bus with either bad parity or uncorrectable ECC error For inbound transactions the bad parity or uncorrectable ECC errors results in the ATU...

Page 98: ...ood done else error create an error log Interrupt the core if enabled On an outbound write request data parity is checked on the data bus D 127 0 The parity bits are checked by first bit XORing the da...

Page 99: ...itions defined within the PCI specification for both requester and target operation Error conditions on the internal bus are caused by an ECC error from the Memory Controller see Section 7 5 ECC Inter...

Page 100: ...ions is taken Set the SERR Asserted bit in the ATUSR When the ATU SERR Asserted Interrupt Mask Bit in the ATUIMR is clear set the SERR Asserted bit in the ATUISR When set no action When the ATU SERR D...

Page 101: ...rms the following actions based on the constraints specified The error is corrected and the ATU completes the transaction on the PCI bus as when no error had occurred Then the transaction is forwarded...

Page 102: ...rrectable data errors occurring at the target for outbound writes However there is no error response for uncorrectable data errors on inbound configuration write completion messages and inbound read c...

Page 103: ...action When the ATU is operating in the PCI X mode the SERR Enable bit in the ATUCMD is set and the Uncorrectable Data Error Recover Enable bit in the PCIXCMD register is clear assert SERR otherwise...

Page 104: ...Parity Error bit in the ATUISR When set no action When the SERR Enable bit in the ATUCMD is set and the Uncorrectable Data Error Recover Enable bit in the PCIXCMD register is clear assert SERR otherw...

Page 105: ...R Asserted bit in the ATUSR When the ATU SERR Asserted Interrupt Mask Bit in the ATUIMR is clear set the SERR Asserted bit in the ATUISR When set no action When the ATU SERR Detected Interrupt Enable...

Page 106: ...rror bits are set 2 7 3 5 2 Split Response Termination As a target the ATU may encounter this error when operating in the PCI X mode Inbound read uncorrectable data errors occur during the Split Respo...

Page 107: ...MR is clear set the PCI Master Parity Error bit in the ATUISR When set no action When the SERR Enable bit in the ATUCMD is set and the Uncorrectable Data Error Recover Enable bit in the PCIXCMD regist...

Page 108: ...it in the ATUSR is set When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear set the PCI Master Parity Error bit in the ATUISR When set no action When the SERR Enable bit in t...

Page 109: ...cleared the ATU retries the transaction by asserting STOP and enqueues the Delayed Write Request cycle to be forwarded to the internal bus PERR is not asserted The Detected Parity Error bit in the ATU...

Page 110: ...ken An Uncorrectable Split Write Data Error message with message class 2h completer error and message index 01h Uncorrectable Split Write Data Error is initiated by the ATU on the PCI bus that address...

Page 111: ...onal actions are taken Set the SERR Asserted bit in the ATUSR When the ATU SERR Asserted Interrupt Mask Bit in the ATUIMR is clear set the SERR Asserted bit in the ATUISR When set no action When the A...

Page 112: ...ver the ATU provides no error response for correctable data errors on inbound read requests In general when the ATU is receiving data from the PCI bus as a target any correctable data errors are corre...

Page 113: ...e error is corrected and the ATU completes the transaction on the PCI bus as when no error had occurred Then the transaction is forwarded to the internal bus normally Update the ECC Control and Status...

Page 114: ...Abort The following actions with given constraints are performed by ATU when a master abort is detected by the PCI initiator interface or the PCI target interface receives a Master Abort Split Comple...

Page 115: ...sage the ATU discards the Split Completion and take no further action 2 7 5 3 Master Aborts Signaled by the ATU as a Target 2 7 5 3 1 Uncorrectable Address Errors The ATU can only signal this error du...

Page 116: ...etion Error Message class 1h bridge error and index 01h Target Abort The following actions with the given constraints are performed by the ATU when a target abort is detected by the PCI initiator inte...

Page 117: ...on the Internal Bus on page 120 for details on the ATU response to an Internal Bus Master Abort 2 7 6 3 2 Internal Bus Target Abort A target abort can be signaled by the ATU during an inbound read req...

Page 118: ...nversely the ATU does not assert DEVSEL for any split completion transaction where either the Requester ID does not match that of the ATU or the Tag does not match that of any currently outstanding sp...

Page 119: ...on bit in the ATUCR has been set and the SERR Enable bit is set in the ATUCMD Note that the SERR manual assertion bits must be cleared manually before they can be set again resulting in SERR asserted...

Page 120: ...given constraints are performed by the ATU when a master abort is detected by the internal master interface during an inbound write request transaction Set the Internal Bus Master Abort bit bit 7 in...

Page 121: ...rget Abort target bit in the ATUISR When set no action Flush the transaction that was master aborted from the ITQ after the target abort is delivered on the PCI interface When operating in the PCI X m...

Page 122: ...TUIMR a disconnect with data is returned to the PCI initiator during the data word that was target aborted on the internal bus In both cases the IRQ is flushed after the completion cycle is performed...

Page 123: ...rity error on the PCI interface Inbound write parity error will be detected and logged by the internal bus target For write data that has to flow through the internal bus bridge the bridge will log th...

Page 124: ...nal SERR In PCI X Mode claim the transaction and complete as when no error had occurred and signal SERR upon uncorrectable error detection All SERR Asserted bit 14 SERR Asserted bit 10 ATUIMR bit 6 Al...

Page 125: ...SERR PCI X Master Parity Error bit 8 Master Parity Error bit 0 ATUIMR bit 2 PCI X SERR Asserted bit 14 SERR Asserted bit 10 ATUIMR bit 6 PCI X N A SERR Detected bit 4 ATUCR bit 9 PCI X Received Split...

Page 126: ...Error PCI X None Inbound Configuration Write Completion Message Correctable Data Error PCI X None Inbound Read Request Correctable Data Error PCI X2 None Inbound Write Request Correctable Data Error...

Page 127: ...None Inbound Configuration Write Completion Message Master Abort PCI X None Outbound Read Request Target Abort All None All Target Abort master bit 12 PCI Target Abort master bit 2 ATUIMR bit 4 PCI X...

Page 128: ...register is set c Table assumes that Data Parity Recovery Enable bit 0 of the PCIXCMD is clear d When a correctable or uncorrectable data error occurs in PCI X Mode 2 the ECC Logging registers consis...

Page 129: ...Abort target bit 1 ATUIMR bit 3 PCI X N A Initiated Split Completion Error Message bit 13 ATUIMR bit 10 Inbound Read Request Target Abort All In the Conventional Mode signal Target Abort In the PCI X...

Page 130: ...ements the MSI capability structure The capability structure includes the Section 4 9 30 MSI Capability Identifier Register Cap_ID on page 450 the Section 4 9 31 MSI Next Item Pointer Register MSI_Nex...

Page 131: ...ber 315037 002US 131 Address Translation Unit PCI X Intel 81341 and 81342 2 9 Internal Interrupts The ATU has 3 internal interrupts that connect to the internal Interrupt Controller Unit ATU Interrupt...

Page 132: ...VPD format 2 10 1 Configuring Vital Product Data Operation By default the 81341 and 81342 VPD functionality is not configured for operation Specifically the VPD Extended Capabilities List Item is not...

Page 133: ...our bytes are always transferred between this register and the VPD storage component 2 10 2 1 Reading Vital Product Data Using the fields defined in the VPD Capabilities List Item the 81341 and 81342...

Page 134: ...le processor is triggered and bit 17 of the ATUISR is set Meanwhile the host processor polls the VPDAR register waiting for the Flag to be cleared Warning When any configuration writes to either the V...

Page 135: ...nently pull the IDSEL pin low on the board to prevent the ATU from claiming configuration transactions Transactions are claimed only when they map into one of the inbound memory BARs 2 11 3 Outbound T...

Page 136: ...acilitate the use of an external driver the CR_FREQ 1 0 pins are driven based on the settings in the PCI X capability field bits 19 16 in the PCI Configuration and Status Register PCSR These output pi...

Page 137: ...lots is necessary When for example a 133 MHz PCI X capable adapter was the sole occupant of a two slot segment then it would be necessary to slow the bus to 100 MHz even though the card reported it co...

Page 138: ...ary bus the PCIXM1_100 pull down strapping ensures that the bus runs at no greater than 100 MHz in PCI X mode regardless of the reported downstream device capabilities When a card is plugged into a si...

Page 139: ...CSR 19 16 contains the initialization pattern captured off the bus during P_RST Table 21 PCI X Initialization Pattern PERR DEVSEL STOP TRDY Modea a 81341 and 81342 supports neither PCI X 533 Mode nor...

Page 140: ...rs Developer s Manual December 2007 140 Order Number 315037 002US When operating as an endpoint in Hot Swap mode HS_SM 0 PCSR 19 16 is set based on the HS_FREQ 1 0 pins For more details see Table 6 HS...

Page 141: ...ible configurations of the dual interface 81341 and 81342 To allow PCI transactions to flow between the two PCI interfaces of the dual interface 81341 and 81342 in a bidirectional manner each of the A...

Page 142: ...000H Inbound Address Translation Window for ATUX IALR2 00000000H IATVR2 00000000H IAUTVR2 00000009H Outbound Address Translation Window for ATUE OUMBAR2 80000009H OUMWTVR2 00000000H Example 3 ATUE as...

Page 143: ...ndpoint INTERFACE_SEL_PCIX can be setup to either 0 or 1 However the function number must be consistent with the function number field programmed in the OUMBAR2 30 28 since this function number is use...

Page 144: ...69 ATU configuration space is function number zero of the 81341 and 81342 single function PCI device Beyond the required 64 byte header format ATU configuration space implements extended register spa...

Page 145: ...pported in the ATUs configuration space To enable the PCI Bus Power Management Interface Specification Revision 1 1 compliance support the Power State Transition interrupt mask in bit 8 of the ATUIMR...

Page 146: ...eaders supported in the ATUs configuration space The first byte at the Extended Configuration Offset D0H is the PCI X Capability Identifier Register Section 2 13 53 This identifies this Extended Confi...

Page 147: ...Register is set to 00H indicating that there are no additional Extended Capabilities Headers supported in the ATUs configuration space The following sections describe the ATU and Expansion ROM configu...

Page 148: ...13 5 ATU Command Register ATUCMD on page 153 006H Section 2 13 6 ATU Status Register ATUSR on page 154 008H Section 2 13 7 ATU Revision ID Register ATURID on page 156 009H Section 2 13 8 ATU Class Cod...

Page 149: ...Capabilities Register APMCR on page 193 09CH Section 2 13 51 ATU Power Management Control Status Register APMCSR on page 194 0A0H Section 4 9 30 MSI Capability Identifier Register Cap_ID on page 450a...

Page 150: ...ndow Translate Value Register 1 OUMWTVR1 on page 218 318H Section 2 13 75 Outbound Upper Memory Window Base Address Register 2 OUMBAR2 on page 219 31CH Section 2 13 76 Outbound Upper 32 bit Memory Win...

Page 151: ...00H Table 24 PCI X Pad Registers Register Offset Section Register Name Acronym Page 2100H Section 2 13 88 PCIX RCOMP Control Register PRCR on page 231 2104H Section 2 13 89 PCIX Pad ODT Drive Strength...

Page 152: ...endor ID to simulate the interface of a standard mechanism currently used by existing application software PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw...

Page 153: ...tribute registers but in all other respects treats the transaction as though it had no error Correctable ECC errors are corrected independent of the state of this bit 05 02 VGA Palette Snoop Enable Th...

Page 154: ...11 02 Target Abort target set when the ATU interface acting as a target terminates the transaction on the PCI bus with a target abort 10 09 012 DEVSEL Timing These bits are read only and define the sl...

Page 155: ...1 are any of the 81341 and 81342 s INT A D signals asserted by the ATU function Note Setting the Interrupt Disable bit to a 1 in bit 10 of ATUCMD has no effect on the state of this bit 02 00 0002 Rese...

Page 156: ...ors Specification Update ATU Revision identifies the revision number PCI IOP Attributes Attributes 7 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro Attribute Legend RV Reserved PR Preserved RS Re...

Page 157: ...ine size is restricted to either 0 8 or 16 DWORDs PCI IOP Attributes Attributes 7 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Writ...

Page 158: ...Function Device Identifies the 81341 and 81342 as a single function or multi function PCI device depending on the setting of the DF_SEL 2 0 strap during P_RST assertion Note The 81341 and 81342 can be...

Page 159: ...is set Setting this bit generates an interrupt to the Intel XScale processor to perform a software BIST function The Intel XScale processor clears this bit when the BIST software has completed with t...

Page 160: ...le Indicator and the Type Indicator Assuming IALR0 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is clea...

Page 161: ...R0 is set to indicate 32 bit addressability the IAUBAR0 register attributes are read only Prior to changing the Type Indicator in the IABAR0 to support 32 bit addressability the IAUBAR0 must be writte...

Page 162: ...Assuming IALR1 is not cleared c Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host configuration the...

Page 163: ...to indicate 32 bit addressability the IAUBAR1 register attributes are read only By default the IAUBAR1 register has read only attributes Prior to changing the Type Indicator in the IABAR1 to support...

Page 164: ...eared e Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host configuration the user should also set the...

Page 165: ...ABAR2 is set to indicate 32 bit addressability the IAUBAR2 register attributes are read only By default the IAUBAR2 register has read only attributes Prior to changing the Type Indicator in the IABAR2...

Page 166: ...ster uniquely identifies the add in board or subsystem vendor PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro...

Page 167: ...ation allows the ERBAR to be programmed per PCI Local Bus Specification Revision 2 3 The Expansion ROM Base Address Register s programmed value must comply with the PCI programming requirements for ad...

Page 168: ...list In the case of the 81341 and 81342 this is the PCI Bus Power Management extended capability as defined by the PCI Bus Power Management Interface Specification Revision 1 1 Table 44 ATU Capabilit...

Page 169: ...zero is a zero so the device requires memory address space Bit three is one so the memory does supports prefetching Scanning upwards starting at bit four bit twenty is the first one bit found The bina...

Page 170: ...bound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus Inbound ATU Upper Base Address Register 2 N A Together with ATU Base Address Re...

Page 171: ...rough 254 FEH are reserved 255 FFH indicates unknown or no connection The operating system or device driver can examine each device s interrupt pin and interrupt line register to determine which syste...

Page 172: ...often a bus master typically requires access to the PCI bus and the duration of a typical transfer when it does acquire the bus This information is useful in determining the values to be programmed in...

Page 173: ...ypically requires access to the PCI bus and the duration of a typical transfer when it does acquire the bus This information is useful in determining the values to be programmed into the bus master la...

Page 174: ...value of 0 in a bit within the IALR0 makes the corresponding bit within the IABAR0 a read only bit which always returns 0 A value of 1 in a bit within the IALR0 makes the corresponding bit within the...

Page 175: ...ss Registers on page 169 The default address allows the ATU to access the internal 81341 and 81342 memory mapped registers 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU perform...

Page 176: ...with a one to one correspondence A value of 0 in a bit within the IALR1 makes the corresponding bit within the IABAR1 a read only bit which always returns 0 A value of 1 in a bit within the IALR1 mak...

Page 177: ...the IABAR1 register s programmed value see Section 2 13 23 Determining Block Sizes for Base Address Registers on page 169 11 01 000H Reserved 00 0 Big Endian Byte Swap enable 0 No swap performed See...

Page 178: ...gister bits 31 to 12 with a one to one correspondence A value of 0 in a bit within the IALR2 makes the corresponding bit within the IABAR2 a read only bit which always returns 0 A value of 1 in a bit...

Page 179: ...s programmed value see Section 2 13 23 Determining Block Sizes for Base Address Registers on page 169 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a byte swap on all...

Page 180: ...always returns 0 A value of 1 in a bit within the ERLR makes the corresponding bit within the ERBAR read write from PCI Table 60 Expansion ROM Limit Register ERLR Bit Default Description 31 12 000000...

Page 181: ...ter s programmed value see Section 2 13 23 Determining Block Sizes for Base Address Registers on page 169 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a byte swap on...

Page 182: ...he Intel XScale processor is not interrupted when P_SERR is detected 08 02 Halt ATU On Error Enable When set and a Data Parity Master Abort or Target Abort error occurs on an Outbound PCI Write Reques...

Page 183: ...or 66 MHz Use P_M66EN to determine frequency 10 PCI X Mode 66 MHz 01 PCI X Mode 100 MHz 00 PCI X Mode 133 MHz Note 81341 and 81342 does not support CompactPCI Hot Swap in PCI X Mode2 25 PCIX_EP PCIX E...

Page 184: ...PCI bus As a Central Resource this field controls the initialization pattern driven on the PCI bus during reset and the value driven on the CR_FREQ 1 0 pins The default value of this field is dependen...

Page 185: ...mer expired Note When the firmware timer is disabled firmware is responsible to clear the Configuration Request Retry bit Otherwise the ATU indefinitely retries all host configuration cycles 06 03 002...

Page 186: ...rrupt 14 02 Detected Correctable Error This bit is set in PCI X Mode 2 only when the 81341 and 81342 detects a single bit ECC error in any phase of a PCI transaction 13 02 Initiated Split Completion E...

Page 187: ...h a target abort 00 02 PCI Master Parity Error Master Parity Error The ATU interface sets this bit under the following conditions The ATU asserted PERR itself or the ATU observed PERR asserted And the...

Page 188: ...g of bit 14 of the ATUISR and generation of the Correctable Error interrupt when in PCI X Mode 2 a correctable error is detected in any phase of a PCI transaction 0 Not Masked 1 Masked 10 02 Initiated...

Page 189: ...or interrupt when a parity error resulting in bit 8 of the ATUSR being set 0 Not Masked 1 Masked 01 02 ATU Inbound Error SERR Enable Controls when ATU asserts when enabled through the ATUCMD SERR on t...

Page 190: ...y list and hence this register is set to 00H Table 67 VPD Capability Identifier Register VPD_Cap_ID Bit Default Description 07 00 03H Cap_Id This field with its 03H value identifies this item in the l...

Page 191: ...mpleted Please see Section 2 10 Vital Product Data on page 132 for more details on how the 81341 and 81342 handles the data transfer 14 0 0000H VPD Address This register is written to set the DWORD al...

Page 192: ...ty list is located at off set B0H Note that the PM_Next_Item_Ptr can be written by the processor Table 71 PM_Capability Identifier Register PM_Cap_ID Bit Default Description 07 00 01H Cap_Id This fiel...

Page 193: ...D1_Support This bit is set to 12 indicating that the 81341 and 81342 supports the D1 Power Management State 8 6 0002 Aux_Current This field is set to 0002 indicating that the 81341 and 81342 has no c...

Page 194: ...he PME signal in any state since PME is not supported by the 81341 and 81342 14 9 00H Reserved 8 02 PME_En This bit is hard wired to read only 02 since this function does not support PME generation fr...

Page 195: ...USPR Bit Default Description 31 0 0000H Scratch Pad Data Entire register is available for application specific purposes PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw...

Page 196: ...pactPCI extended capabilities header PCI IOP Attributes Attributes 7 4 0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Write RC Read Cle...

Page 197: ...96 1 12 Enable Relaxed Ordering When set the 81341 and 81342 may set the relaxed ordering bit in the Requester Attributes of Transactions 0 02 Uncorrectable Data Error Recovery Enable The device drive...

Page 198: ...ompletion with this device s Requester ID is received Once set this bit remains set until software writes a 1 to this location 0 no unexpected Split Completion has been received 1 an unexpected Split...

Page 199: ...rdware The system must assign a device number other than 00h 00h is reserved for the source bridge The function uses this number as part of its Requester ID and Completer ID Each time the function is...

Page 200: ...rected and are treated as uncorrectable errors including the setting of status bits and assertion of error indicator signals on the bus Disabling single bit error correction enhances the error detecti...

Page 201: ...bled to latch information about an ECC error When the 81341 and 81342 detects an error it latches the phase of the error in this register and stores status information for the error in this register a...

Page 202: ...onal correctable ECC error has been detected 1 One or more additional correctable ECC errors have been detected 1 0 002 Reserved Table 80 ECC Control and Status Register ECCCSR Sheet 3 of 3 Bit Defaul...

Page 203: ...e ECC Control and Status Register ECCCSR ECC First Address Register ECCFAR ECC Second Address Register ECCSAR and ECC Attribute Register ECCAR report the actual transaction that has the error For exam...

Page 204: ...nd Status Register ECCCSR ECC First Address Register ECCFAR ECC Second Address Register ECCSAR and ECC Attribute Register ECCAR report the actual transaction that has the error For example when the Sp...

Page 205: ...error the information regarding the Split Completion is reported 2 13 61 CompactPCI Hot Swap Capability ID Register The following register block provides support of CompactPCI Hot Swap functionality T...

Page 206: ...o Retry Type 0 configuration cycles bit 2 of PCSR Typically the Intel XScale processor would be enabled to boot immediately following P_RST assertion in this case bit 1 of PCSR as well Please see Sect...

Page 207: ...de asserts P_ENUM when currently asserted and is then armed for a possible future extraction event EXT bit assertion is enabled 06 0b EXT Pending EXTraction of board 81341 and 81342 sets this bit to a...

Page 208: ...T bits of this register When 1b 81341 and 81342 does not assert P_ENUM under any circumstances 00 0b DHA Device Hiding Armed When 1b When HS_SM 0b and LSTAT 1b Switch open and the LOO bit 1b 81341 and...

Page 209: ...Type Indicator for 64 bit addressability This is the default for IABAR3 Assuming a non zero value is written to IALR3 the user may set the Prefetchable Indicator or the Type Indicator a Since non pre...

Page 210: ...t addressability the IAUBAR3 register attributes are read only By default the IAUBAR3 register has read only attributes Prior to changing the Type Indicator in the IABAR3 to support 32 bit addressabil...

Page 211: ...I Local Bus Specification Revision 2 3 for additional information on programming base address registers Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register bits 31 to 12 with a...

Page 212: ...egister s programmed value see Section 2 13 23 Determining Block Sizes for Base Address Registers on page 169 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a byte swap...

Page 213: ...s set to 0000H see I O Transactions on page 76 Table 92 Outbound I O Base Address Register OIOBAR Bit Default Description 31 12 0 FFFBH Outbound I O Base Address This value represents bits 35 to 16 of...

Page 214: ...Register OIOBAR with the a fixed length of 64 Kbytes Table 93 Outbound I O Window Translate Value Register OIOWTVR Bit Default Description 31 16 0000H Outbound I O Window Translate Value Used to conve...

Page 215: ...matches OUMBAR0 3 0 30 28 0002 Outbound Window 0 Function Number Mapping Errors with Outbound Memory Window 0 transactions PCI or Internal Bus is associated with the function number contained in this...

Page 216: ...s space When this register is all zero then a SAC is generated on the PCI bus Table 95 Outbound Upper 32 bit Memory Window Translate Value Register 0 OUMWTVR0 Bit Default Description 31 00 0000 0000H...

Page 217: ...32 matches OUMBAR1 3 0 30 28 0002 Outbound Window 1 Function Number Mapping Errors with Outbound Memory Window 1 transactions PCI or Internal Bus is associated with the function number contained in th...

Page 218: ...s space When this register is all zero then a SAC is generated on the PCI bus Table 97 Outbound Upper 32 bit Memory Window Translate Value Register 1 OUMWTVR1 Bit Default Description 31 00 0000 0000H...

Page 219: ...matches OUMBAR2 3 0 30 28 0002 Outbound Window 2 Function Number Mapping Errors with Outbound Memory Window 2 transactions PCI or Internal Bus is associated with the function number contained in this...

Page 220: ...pace When this register is all zero then a SAC is generated on the PCI bus Table 99 Outbound Upper 32 bit Memory Window Translate Value Register 2 OUMWTVR2 Bit Default Description 31 00 0000 0000H The...

Page 221: ...32 matches OUMBAR3 3 0 30 28 0002 Outbound Window 3 Function Number Mapping Errors with Outbound Memory Window 3 transactions PCI or Internal Bus is associated with the function number contained in t...

Page 222: ...space When this register is all zero then a SAC is generated on the PCI bus Table 101 Outbound Upper 32 bit Memory Window Translate Value Register 3 OUMWTVR3 Bit Default Description 31 00 0000 0000H...

Page 223: ...e a Type 0 configuration cycle the OCCAR should always be loaded based on the PCI X definition for the Type 0 configuration cycle address When operating in Conventional mode the 81341 and 81342 clears...

Page 224: ...re errors get logged For 81341 and 81342 the function number should be 0 for endpoint usage and match the ATUX function number readable in PCI X Status Register PCIXSR for Root Complex modes Table 103...

Page 225: ...PCIECSR bit 0 is set 0000 Address Parity Error 0001 Data Parity Error 0010 Master Abort 0011 Target Abort 0100 Received Split Completion Error Message 0101 Unexpected Split Completion 0110 Split Compl...

Page 226: ...page 99 Note The PCI Interface Error Control and Status Register PIECSR PCI Interface Error Address Register PCIEAR and PCI Interface Error Upper Address Register PCIEUAR report the original transact...

Page 227: ...and Status Register PIECSR PCI Interface Error Address Register PCIEAR and PCI Interface Error Upper Address Register PCIEUAR report the original transaction when an error is detected on the current...

Page 228: ...error by reading this register and decoding the contents of the PCIECSR For error details see Section 2 7 ATU Error Conditions on page 99 Table 108 PCI Interface Error Context Address Register PCIECA...

Page 229: ...ing the bus 1 Bus is always parked on 81341 and 81342 07 02 Reserved 06 02 ATU Ring Allocation Priority ring allocation for 81341 and 81342 ATU requests 0 The ATU is in the low priority ring of the in...

Page 230: ...locks allotted to the current agent after which the arbiter grants another agent that is requesting the bus Table 110 Multi Transaction Timer MTT Bit Default Description 07 03 00H Timer Count Value MT...

Page 231: ...ge 2 b01 5 Reference 2 b10 5 Reference 08 07 012 Drive strength select for ODT RCOMP pad 2 b00 103 0 ohms 2 b01 110 0 ohms 2 b10 120 0 ohms 06 04 0102 Drive strength select for RCOMP pad dedicated 3 3...

Page 232: ...verride Values Registers PPODSMOVR Bit Default Description 31 14 00000H Reserved 13 08 1000002 N ODT drive strength manual override values for PCIX pad 07 06 002 Reserved 05 00 1000002 P ODT drive str...

Page 233: ...efault Description 31 28 0H Reserved 27 24 10002 N slew rate manual override values for PCIX pad 23 20 00002 Reserved 19 16 10002 P slew rate manual override values for PCIX pad 15 14 002 Reserved 13...

Page 234: ...Description 31 28 0H Reserved 27 24 10002 N slew rate manual override values for PCIX pad 23 20 00002 Reserved 19 16 10002 P slew rate manual override values for PCIX pad 15 14 002 Reserved 13 08 100...

Page 235: ...bound or outbound transactions and processes them simultaneously During inbound transactions the ATU converts PCI addresses initiated by a PCI Express Requester to internal bus addresses and initiates...

Page 236: ...n 1 0a Additionally the ATU includes three PCI Express Extended capability headers that implement Advanced Error Handling Device Serial Number and Power Budgeting as defined in the PCI Express Base Sp...

Page 237: ...ntries Inbound Non Posted Header INPHQ 8Entries Outbound Posted Data Queue OPDQ 4KBytes Outbound Completion Data Queue OCPLDQ 4KBytes Outbound Completion Header Queue OCPLHQ 8Entries Outbound Posted H...

Page 238: ...y should enable straight routing between the component and the PCI Express card edge connector The lane reversal feature can be utilized to simplify applications where this component is connected to t...

Page 239: ...pending until one of the earlier active transactions is completed Each active outbound read request may be fragmented into sub requests based on the MAX_READ_REQUEST_SIZE parameter programmed in the...

Page 240: ...sactions generated by the core processor is determined by the internal bus address and the fixed outbound windowing scheme ATU supports all four address spaces defined within the PCI Express architect...

Page 241: ...es Yes Read MRdLk 00 01 0 0001 Unsupported Request No N A MWr 10 11 0 0000 Yes Yes Write IORd 00 0 0010 Yes Yes Read IOWr 10 0 0010 Yes Yes Write CfgRd0 00 0 0100 Yes Yes Read CfgWr0 10 0 0100 Yes Yes...

Page 242: ...n data queue OCPLDQ The INPQ is capable of holding up to 8 non posted requests and any associated data Operation of the internal bus is defined in Section 6 0 System Controller SC and Internal Bus Bri...

Page 243: ...gister In the case of 3DW headers the upper 32 bits of the address is assumed to be 0000_0000h during address comparison The algorithm for detection is Figure 25 shows an example of inbound address de...

Page 244: ...ed on page 247 Figure 26 shows an inbound translation example for 32 bit addressing This example would hold true for an inbound transaction from PCI Express Link Equation 9 Inbound Translation 81341 a...

Page 245: ...bus when IPHQ has at least one entry When the internal bus is granted the internal bus master interface initiates the write transaction by driving the translated address onto the internal bus For deta...

Page 246: ...pletion Data Queue A zero length read memory read request of 1 DW with no bytes enabled has no side effects Once a completion transaction has started it continues until one of the following is true Th...

Page 247: ...on ID Routed The 81341 and 81342 ATU only accepts Type 0 configuration requests with a function number of zero when bit 7 of the ATUHTR see Section 3 16 11 ATU Header Type Register ATUHTR on page 306...

Page 248: ...then when a second vendor specific message transaction reaches the head of the IPHQ it stalls until the message registers are freed by clearing the Message Received bit in the ATUISR Since messages ar...

Page 249: ...et data returned into the Inbound Completion Data Queue ICPLDQ Refer to Section 3 8 2 for details of outbound queue architecture Outbound configuration transactions use a special outbound port structu...

Page 250: ...y of the 64 Gbyte Internal Bus address space The response of the ATU to Outbound Transactions is globally controlled by the Outbound Enable bit in the ATU Configuration Register as well as the Bus Mas...

Page 251: ...l to 01H Outbound Upper Memory Base Address Register 1 OUMBAR1 Default Value equal to 02H Outbound Upper Memory Base Address Register 2 OUMBAR2 Default Value equal to 03H Outbound Upper Memory Base Ad...

Page 252: ...2 Order Number 315037 002US Figure 27 4 Gbyte Section 0 of the Internal Bus Memory Map Peripheral Memory Mapped Registers 0 0000 0000H ADDRESS Address Space Used for Other Resources Code Data External...

Page 253: ...ation Cycle Address Register OCCAR See Section 3 16 for details on outbound translation register definition and programming constraints The translation algorithm used as stated is very similar to inbo...

Page 254: ...nsactions use the function number field specified in the Outbound I O Base Address Register OIOBAR on page 376 Outbound transactions targeting the outbound memory windows utilize the Outbound Window x...

Page 255: ...abled for transmission on the PCI Express Link The PCI interface is responsible for completing the outbound write transaction with the PCI address translated from the OPHQ and the data in the OPDQ The...

Page 256: ...of the ONPQ has at least one entry and the ordering rules are satisfied Once the request is issued the Transaction Pending bit is set in the PCI Express Device Status Register PE_DSTS When a Completi...

Page 257: ...saction with the address in the associated address register When the data register is accessed the address is pulled from the Outbound Configuration Cycle Address Register OCCAR to generate the TLP he...

Page 258: ...s cycles 1 Write outbound message transaction header registers 0 3 2 Write the data to the outbound message transaction payload register This write causes the generation of the message TLP on the PCI...

Page 259: ...Upper Memory BAR 0 3 OUMBAR0 3 Note The Messaging Unit MU Memory is mapped in PCI Window 0 ATU Base Address Register 0 along with the MSI X table structures Byte swapping should not be enabled for BAR...

Page 260: ...within each DWORD for PCI to Memory Read Write DMA transfers Figure 30 Outbound Byte Swapping for Transaction with Byte Count of 1 Figure 31 Outbound Byte Swapping for Transactions with Byte Count of...

Page 261: ...the PCI system and the 81341 and 81342 and notifies the respective system when new data arrives The MU is located on the south internal bus of the 81341 and 81342 and is accessed via the ATU The MU is...

Page 262: ...ow power state from an End Point or Upstream Port RC PME_Turn_Offa Notification of pending turn off of link clock and power RC Generated from PEMCSR PM_PMEb PME message conveying the ID of the PME ori...

Page 263: ...register and interrupt the core Vendor Defined Message Type 0 1 Vendor Specific Message It is used by devices to communicate with SRL device core RC End Point Log in Inbound Vendor Message Register an...

Page 264: ...ated device The code can be discarded once executed Expansion ROM registers are described in Section 3 16 22 The inbound ATU supports an inbound Expansion ROM window which works like the inbound trans...

Page 265: ...rnal bus The corresponding header queue IPHQ is capable of holding 8 entries The following rules apply to the PCI Express Link interface and govern the acceptance of data into inbound posted queues Po...

Page 266: ...on Queue Structure The inbound completion queue provides insures space for all outstanding outbound read requests This queue is 4KB in size and is used to order the completion data before returning it...

Page 267: ...t or target abort cases For outbound reads the address is entered into the OTQ when not full and a split response termination is signaled to the requester on the internal bus Read data is fetched and...

Page 268: ...rite requests are not maintained as indicated in Table 126 on page 269 For best performance the user should designate the two Outbound Memory Windows as non cachable and bufferable from theIntel XScal...

Page 269: ...multiple transactions may exist within the IPHQ and the corresponding IPDQ at any point in time The ordering of these transactions is based on a time stamp basis Transactions entering the queue are s...

Page 270: ...wo transactions at the head of the queues moving data in an inbound direction are now Transaction C an inbound write and Transaction B an outbound read completion Ordering states that an inbound write...

Page 271: ...o Not Assign Token Allow previous Transaction to Complete No Assign Token Inbound Completion in ICPLHQ Is the relaxed order bit set in the header and the Enable Relaxed Ordering bit set in the ATUCR Y...

Page 272: ...or an inbound write request the ATU computes and appends address parity and data parity before placing the TLP in the inbound queues When an ECRC violation is detected the packet is treated as when an...

Page 273: ...s good done else error create an error log Interrupt the core if enabled On an outbound request with data data parity is checked on the data bus D 127 0 The parity bits are checked by first bit XORing...

Page 274: ...and have different effects depending on the error Error conditions and their effects are described in the following sections PCI Express error conditions and the action taken on the link are defined w...

Page 275: ...ions are still logged and reported by the target device Note When the severity for the error is programmed to fatal in the PCI Express Uncorrectable Error Severity ERRUNC_SEV register then it is not a...

Page 276: ...y When 81341 and 81342 is operating as Endpoint and ATUE receives Assert_INTx Deassert_INTx messages Assert_INTx Deassert_INTx messages do not use default Traffic Class TC0 Power Management messages d...

Page 277: ...estor Note When the severity setting in PCI Express Uncorrectable Error Severity ERRUNC_SEV register is fatal this is not an Advisory Error and an ERR_FATAL is sent to the root complex 3 9 1 5 Complet...

Page 278: ...get valid data When firmware decides to stop retrying the transaction it must escalate the error by setting the Generate ERR_NONFATAL bit in the PCI Express Advisory Error Control Register PIE_AEC Not...

Page 279: ...ernal bus errors The tables assume that all error reporting is enabled through the appropriate command registers unless otherwise noted Example A poisoned TLP is received Depending on the setting in t...

Page 280: ...TUSR 14 PE_DSTS 3 PE_DSTS 2 or 1 ERRUNC_STS 20 PIE_STS 20 ATUISR 10 8 ATUCMD 8 PE_DCTL 2 or 1 ATUIMR 8 ERRUNC_MSK 20 PIE_MSK 20 Completion Timeout Requester Send ERR_FATAL ERR_NONFATAL to Root Complex...

Page 281: ...R to Root Complex PE_DSTS 0 ERRCOR_STS 12 ATUISR 9 PE_DCTL 0 ERRCOR_MSK 12 ATUIMR 9 REPLAY_NUM Rollover Transmitter Send ERR_COR to Root Complex PE_DSTS 0 ERRCOR_STS 8 ATUISR 9 PE_DCTL 0 ERRCOR_MSK 8...

Page 282: ...s Register Unit Interrupt Mask Bits Internal Bus Errors Master Abort on inbound requests Signal Completer Abort See Completer Abort above See Completer Abort above Completer Abort and ATUISR 5 Complet...

Page 283: ...s designed to natively support both Hot Plug and hot remove of devices This section defines the usage model defined for all the ATU ATU supports the receipt and generation of Hot Plug messages via the...

Page 284: ...ct types of reset cold warm and hot The fundamental reset that occurs following initial power on is considered a hot reset The assertion of the PRST or WARM_RST pins are considered warm resets The rec...

Page 285: ...SI Next Item Pointer Register MSI_Next_Ptr on page 451 the Section 4 9 33 Message Address Register Message_Address on page 453 the Section 4 9 34 Message Upper Address Register Message_Upper_Address o...

Page 286: ...format 3 13 1 Configuring Vital Product Data Operation By default the 81341 and 81342 VPD functionality is not configured for operation Specifically the VPD Extended Capabilities List Item are not dis...

Page 287: ...0 Four bytes are always transferred between this register and the VPD storage component 3 13 2 1 Reading Vital Product Data Using the fields defined in the VPD Capabilities List Item the 81341 and 813...

Page 288: ...Scale processor is triggered and bit 17 of the ATUISR is set Meanwhile the host processor polls the VPDAR register waiting for the Flag to be cleared Warning When any configuration writes to either th...

Page 289: ...Express hierarchy When operating as a Root Complex the ATU behaves as a single function device and only claims transactions for the ATU function This means that the BARs and control signals from othe...

Page 290: ...ossible configurations of the dual interface 81341 and 81342 To allow PCI transactions to flow between the two PCI interfaces of the dual interface 81341 and 81342 in a bidirectional manner each of th...

Page 291: ...000000H Inbound Address Translation Window for ATUX IALR2 00000000H IATVR2 00000000H IAUTVR2 00000009H Outbound Address Translation Window for ATUE OUMBAR2 80000009H OUMWTVR2 00000000H Example 7 ATUE...

Page 292: ...an endpoint INTERFACE_SEL_PCIX can be setup to either 0 or 1 However the function number must be consistent with the function number field programmed in the OUMBAR2 30 28 as this function number is u...

Page 293: ...l configuration read and write transactions is accepted on the internal bus as 32 bit transactions Refer to Chapter 21 0 Peripheral Registers The ATU is programmed via a Type 0 configuration command o...

Page 294: ...Management Interface Specification Revision 1 1 compliance support the Power State Transition interrupt mask in bit 8 of the ATUIMR needs to be cleared It is the configuration software s responsibili...

Page 295: ...Pointer Register Section 3 16 56 which indicates the configuration offset of an additional Extended Capabilities Header when supported In the ATU the Next Item Pointer Register is set to 00H by defaul...

Page 296: ...Extended Capabilities Headers supported in the ATUs configuration space The following sections describe the ATU and Expansion ROM configuration registers Configuration space consists of 8 16 24 and 32...

Page 297: ...D000H Table 135 ATU PCI Configuration Register Space Sheet 1 of 4 Internal Bus Address Offset ATU PCI Configuration Register Section Name Page 000H Section 3 16 3 ATU Vendor ID Register ATUVID on pag...

Page 298: ...l Status Register PEMCSR on page 337 084H Section 3 16 45 PCI Express Link Control Status Register PELCSR on page 338 090H Section 3 16 46 VPD Capability Identifier Register VPD_Cap_ID on page 339 091...

Page 299: ...ess Advanced Error Header Log ADVERR_LOG1 on page 366 124H Section 3 16 78 PCI Express Advanced Error Header Log ADVERR_LOG2 on page 366 128H Section 3 16 79 PCI Express Advanced Error Header Log ADVE...

Page 300: ...ister 0 OVMHR0 on page 393 364H Section 3 16 111 Outbound Vendor Message Header Register 1 OVMHR1 on page 394 368H Section 3 16 112 Outbound Vendor Message Header Register 2 OVMHR2 on page 395 36CH Se...

Page 301: ...to simulate the interface of a standard mechanism currently used by existing application software PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro...

Page 302: ...to a poisoned TLP received from PCI Express When cleared parity checking is disabled Note When the bit is cleared but the Poisoned TLP Mask is cleared in the PCI Express Uncorrectable Error Mask ERRU...

Page 303: ...10 09 002 DEVSEL Timing Does not apply to PCI Express Hard wired to 0 08 02 Master Data Parity Error This bit is set by the ATU when its Parity Error Enable bit is set and either of the following two...

Page 304: ...Update ATU Revision identifies the 81341 and 81342 revision number PCI IOP Attributes Attributes 7 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro Attribute Legend RV Reserved PR Preserved RS Rea...

Page 305: ...cription 07 00 00H ATU Cacheline Size specifies the system cacheline size in DWORDs Note This field is read write for legacy compatibility purposes but has no impact on any PCI Express device function...

Page 306: ...ction Device Identifies the 81341 and 81342 as a single function or multi function PCI device depending on the setting of the DF_SEL 2 0 strap during P_RST assertion Note The 81341 and 81342 can be co...

Page 307: ...s set Setting this bit generates an interrupt to the Intel XScale processor to perform a software BIST function The Intel XScale processor clears this bit when the BIST software has completed with the...

Page 308: ...ator and the Type Indicator Assuming IALR0 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prio...

Page 309: ...is set to indicate 32 bit addressability the IAUBAR0 register attributes are read only Prior to changing the Type Indicator in the IABAR0 to support 32 bit addressability the IAUBAR0 must be written w...

Page 310: ...tching Scanning upwards starting at bit four bit twenty is the first one bit found The binary weighted value of this bit is 1 048 576 indicated that the device requires 1 Mbyte of memory space The ATU...

Page 311: ...I Express Link Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines the inbound translation window 1 from the PCI Express Link Inbound ATU Upper Base Address Register 1 N A Togethe...

Page 312: ...IALR1 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host configuration the user sho...

Page 313: ...indicate 32 bit addressability the IAUBAR1 register attributes are read only By default the IAUBAR1 register has read only attributes Prior to changing the Type Indicator in the IABAR1 to support 32...

Page 314: ...he Type Indicator Assuming IALR2 is not cleared a Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary when the Prefetchable Indicator is cleared prior to host...

Page 315: ...ty or the Memory Space indicator of IABAR2 is set indicating I O space the IAUBAR2 register attributes are read only By default the IAUBAR2 register has read only attributes Prior to changing the Type...

Page 316: ...uely identifies the add in board or subsystem vendor PCI IOP Attributes Attributes 15 12 8 4 0 rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro Attribute...

Page 317: ...rogrammed per PCI Local Bus Specification Revision 2 3 The Expansion ROM Base Address Register s programmed value must comply with the PCI programming requirements for address alignment Refer to the P...

Page 318: ...the case of the 81341 and 81342 this is the PCI Express Link Power Management extended capability as defined by the PCI Bus Power Management Interface Specification Revision 1 1 Table 157 ATU Capabil...

Page 319: ...hrough 254 FEH are reserved 255 FFH indicates unknown or no connection Operating system or device driver can examine each device interrupt pin and interrupt line register to determine which system int...

Page 320: ...scription 07 00 01H Interrupt Used A value of 01H signifies that the ATU interface unit uses the INTA legacy interrupt message PCI IOP Attributes Attributes 7 4 0 rw ro rw ro rw ro rw ro rw ro rw ro r...

Page 321: ...register does not apply to PCI Express Table 161 ATU Maximum Latency Register ATUMLAT Bit Default Description 07 00 00H This register does not apply to PCI Express Hard wired to 0 PCI IOP Attributes A...

Page 322: ...hin the IALR0 makes the corresponding bit within the IABAR0 a read only bit which always returns 0 A value of 1 in a bit within the IALR0 makes the corresponding bit within the IABAR0 read write from...

Page 323: ...ss Registers on page 310 The default address allows the ATU to access the internal 81341 and 81342 memory mapped registers 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU perform...

Page 324: ...orrespondence A value of 0 in a bit within the IALR1 makes the corresponding bit within the IABAR1 a read only bit which always returns 0 A value of 1 in a bit within the IALR1 makes the corresponding...

Page 325: ...egister s programmed value see Section 3 16 15 Determining Block Sizes for Base Address Registers on page 310 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU performs a byte swap...

Page 326: ...to one correspondence A value of 0 in a bit within the IALR2 makes the corresponding bit within the IABAR2 a read only bit which always returns 0 A value of 1 in a bit within the IALR2 makes the corr...

Page 327: ...to be less than 1 Kbyte Hardware uses the PCI Address bits 09 08 as captured on the PCI address bus to drive the internal bus address 09 08 Table 169 Inbound ATU Translate Value Register 2 IATVR2 Bit...

Page 328: ...ranslate Value Register 2 IAUTVR2 Bit Default Description 31 04 000 0000H Reserved 3 0 0H Inbound Upper ATU Translation Value 2 This value represents bits 35 to 32 of the internal bus address used to...

Page 329: ...ith the ERBAR register s programmed value see Section 3 16 15 Determining Block Sizes for Base Address Registers on page 310 11 01 000H Reserved 00 0 Big Endian Byte Swap enable When set the ATU perfo...

Page 330: ...Outbound Completion Size This bit controls how completions are returned on the PCI Express interface 0 Max Payload Size setting is used to format completions Once enough data has accumulated to reach...

Page 331: ...5 02 Outbound Transaction Queue Busy 0 Outbound Transaction Queue Empty 1 Outbound Transaction Queue Busy Note This tracks outbound transactions and includes the Outbound Non Posted Outbound Posted an...

Page 332: ...is set the PCI Express interface of the 81341 and 81342 responds to all configuration cycles with a Completion Retry Status CRS condition When clear the 81341 and 81342 responds to the appropriate co...

Page 333: ...PE_RCR on page 357 Generates the ATU Inbound Message Interrupt 26 0 Hot Plug Message Received This bit set when a Hot Plug message is received that changes the value of the Attention Indicator Status...

Page 334: ...S register Note This read only bit is an OR of the unmasked PIE_STS bits Generates the ATU Error Interrupt 09 0 Correctable Error Message Transmitted Indicates a ERR_COR message was sent to the Root C...

Page 335: ...n Status is received by any function Generates the ATU Error Interrupt 00 0 Master Data Parity Error Interrupt Set when the Parity Error Response is enabled and any function transmits a Poisoned Write...

Page 336: ...interrupt is masked 12 0 Root System Error Interrupt Mask When 1 the interrupt is masked 11 0 Reserved 10 0 Reserved Note ATUISR 10 is controlled by the PCI Interface Error Mask PIE_MSK register 09 0...

Page 337: ...ed 01 On 10 Blink 11 Off Note These bits are updated regardless of the state of the Hot Plug Interrupt Mask in the ATUIMR 27 16 000H Reserved 15 02 Attention Button Pressed Control When this bit is as...

Page 338: ...ambling Disabled Status 0 Scrambling Active 1 Scrambling Disabled 4 Loopback Status 0 Loopback Disabled 1 Loopback Enabled 3 0 Disable Scrambling This controls the disable scrambling bit in the TS1 Or...

Page 339: ...hence this register is set to 00H Table 180 VPD Capability Identifier Register VPD_Cap_ID Bit Default Description 07 00 03H Cap_Id This field with its 03H value identifies this item in the linked lis...

Page 340: ...Please see Section 3 13 Vital Product Data on page 286 for more details on how the 81341 and 81342 handles the data transfer 14 0 0000H VPD Address This register is written to set the DWORD aligned by...

Page 341: ...ext capability MSI X capability list is located at off set B0H Note that the PM_Next_Item_Ptr can be written by the processor Table 184 PM_Capability Identifier Register PM_Cap_ID Bit Default Descript...

Page 342: ...gement State 9 12 D1_Support Set to 12 indicating that the 81341 and 81342 supports the D1 Power Management State 8 6 0002 Aux_Current This field is set to 0002 indicating that the 81341 and 81342 has...

Page 343: ...342 Hard wired 0 14 9 00H Reserved 8 02 PME_En This bit is hard wired to read only 02 since this function does not support PME generation from any power state 7 2 0000002 Reserved 1 0 002 Power State...

Page 344: ...is available for application specific purposes PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 345: ...ialized at P_RST assertion to Retry Type 0 configuration cycles bit 2 of PCSR Typically the Intel XScale processor would be enabled to boot immediately following P_RST assertion in this case bit 1 of...

Page 346: ...ociated with this port is connected to a slot Only valid for root complex and switch downstream ports Hard wired to 0 Set to 1 for root complex this bit is initialized via strapping options 7 4 0000 o...

Page 347: ...emented on the card or module 13 0 Attention Indicator Preset on Device When set indicates that an Attention Indicator is implemented on the card or module 12 0 Attention Button Present on Device When...

Page 348: ...om functions Hard wired to 0 8 0 Extended Tag Field Enable 81341 and 81342 does not generate 8 bit tags Hard wired to 0 7 5 000 Max_Payload_Size This field sets maximum TLP payload size for the device...

Page 349: ...from the point of view of the respective function For a Root Port the reporting of non fatal errors is internal to the root No external ERR_NONFATAL message is generated 0 0 Correctable Error Reporti...

Page 350: ...ntrol register For devices supporting Advanced Error Handling errors are logged in this register regardless of the settings of the correctable error mask register For a multi function device each func...

Page 351: ...eserved 17 15 111b L1 Exit Latency Active State L1 Transition not supported 14 12 001b L0s Exit Latency 64ns 128ns 11 10 01b Active State Link PM Support 9 4 08H Maximum Link Width This device support...

Page 352: ...k are operating with a distributed common reference clock This bit used to report the correct L0s and L1 Exit Latencies in the PCIE_LCAP register 5 0 Retrain Link As an end point this bit is hard wire...

Page 353: ...read only bit indicates that Link training is in progress Hardware clears this bit once Link training is complete 10 0 Link Training Error As an endpoint this bit is hard wired to 0 For root complex t...

Page 354: ...registers should be initialized to 0 for ports connected to devices that are integrated on the system board 18 17 00b Reserved 16 15 00b Slot Power Limit Scale 14 7 00H Slot Power Limit Value 6 0 Hot...

Page 355: ...s Table 199 PCI Express Slot Control Register PE_SCR Bit Default Description 15 11 0H Reserved 10 0 Power Controller Control 9 8 00 Power Indicator Control 7 6 00 Attention Indicator Control 5 0 Hot P...

Page 356: ...in case a software solution can be implemented using the GPIO pins Table 200 PCI Express Slot Status Register PE_SSTS Bit Default Description 15 7 0H Reserved Zero 6 0 Presence Detect State 5 0 MRL S...

Page 357: ...when a fatal error ERR_FATAL message is received or a fatal error is detected by ATU This is only valid when operating as the root complex 1 0 System Error on Non Fatal Error Enable When set the ATU...

Page 358: ...us bit again and updating the Requester ID appropriately The ATU only supports a single PME at a time This bit hard wired to 0 16 0 PME Status This bit indicate that PME was asserted by the requestor...

Page 359: ...he next capability or program with 1F0H to bypass the DSN and point to Power Budgeting as the next capability 19 16 1H Advanced Error Capability Version Number PCI Express Advanced Error Reporting Ext...

Page 360: ...cted Completion As a receiver set whenever a completion is received that does not match the 81341 and 81342 s requestor ID or outstanding Tag The Header is logged 15 0 Completer Abort As a completer s...

Page 361: ...is masked 18 0 Malformed TLP Error Mask When 1 error reporting is masked 17 0 Receiver Overflow Error Mask When 1 error reporting is masked 16 0 Unexpected Completion Error Mask When 1 error reportin...

Page 362: ...tion 31 21 0 Preserved 20 0 Unsupported Request Error Status Severity 19 0 ECRC Check Severity 18 1 Malformed TLP Severity 17 1 Receiver Overflow Severity 16 0 Unexpected Completion Severity 15 0 Comp...

Page 363: ...al Error Status 12 0 Replay Timer Timeout Status Set whenever a replay timer timeout occurs 11 9 0 Reserved Software must write 0 to these bits 8 0 REPLAY_NUM Rollover Status Set whenever the replay n...

Page 364: ...ctable Error Mask ERRCOR_MSK Bit Default Description 31 14 0 Preserved 13 1 Advisory Non Fatal Error Mask this bit is set by default to enable compatibility with software that does not comprehend Role...

Page 365: ...l all bits in the ERRUNC_STS register are cleared PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr pr...

Page 366: ...ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Attribute Legend RV Reserved PR Preserved RS Read Set RW Read W...

Page 367: ...ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S A...

Page 368: ...rrectable error messages have been received 5 0 Non Fatal Error Messages Received This bit set when one or more Non Fatal Uncorrectable error messages have been received 4 0 First Uncorrectable Fatal...

Page 369: ...ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro rw ro S S S S S S S S S S S...

Page 370: ...31 0 0H PCI Express Device Serial Number Lower DW This register represents bits 31 to 0 of the EUI 64 identifier PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw ro rw ro rw ro rw ro rw ro rw...

Page 371: ...nes the behavior when receiving a posted transaction that has poisoned data 0 Do not treat as an Advisory Error Send ERR_NONFATAL to root complex when error is detected 1 Treat as Advisory Error and s...

Page 372: ...ved RS Read Set RW Read Write RC Read Clear RO Read Only NA Not Accessible Internal Bus Address Offset 1F0H Table 222 Power Budgeting Data Select Register PWRBGT_DSEL Bit Default Description 31 8 00_0...

Page 373: ...he power management state of the operating condition being described 00 D0 01 D1 10 D2 11 D3 A device returns 11b in this field and Aux or PME Aux in the Type register to specify the D3 Cold PM state...

Page 374: ...get for the device is included within the system power budget Reported Power Budgeting Data for this device should be ignored by software for power budgeting decisions when this bit is set PCI IOP Att...

Page 375: ...umbers for 81341 and 81342 Data Select PWRBGT_INFOx Register Offset Data Select PWRBGT_INFOx Register Offset 00h 0 200H 0Ch 12 230H 01h 1 204H 0Dh 13 234H 02h 2 208H 0Eh 14 238H 03h 3 20CH 0Fh 15 23CH...

Page 376: ...16 from the Outbound I O Window Translate Value Register OIOWTVR Table 226 Outbound I O Base Address Register OIOBAR Bit Default Description 31 12 0 FFFDH Outbound I O Base Address This value represe...

Page 377: ...Register OIOBAR with the a fixed length of 64 Kbytes Table 227 Outbound I O Window Translate Value Register OIOWTVR Bit Default Description 31 16 0000H Outbound I O Window Translate Value Used to con...

Page 378: ...A 35 32 matches OUMBAR0 3 0 30 28 0002 Outbound Window 0 Function Number Mapping Errors with Outbound Memory Window 0 transactions PCI or Internal Bus is associated with the function number contained...

Page 379: ...this register is all zero then a 3DW header is generated on the PCI Express Link Table 229 Outbound Upper 32 bit Memory Window Translate Value Register 0 OUMWTVR0 Bit Default Description 31 00 0000 0...

Page 380: ...matches OUMBAR1 3 0 30 28 0002 Outbound Window 1 Function Number Mapping Errors with Outbound Memory Window 1 transactions PCI or Internal Bus is associated with the function number contained in this...

Page 381: ...this register is all zero then a 3DW header is generated on the PCI Express Link Table 231 Outbound Upper 32 bit Memory Window Translate Value Register 1 OUMWTVR1 Bit Default Description 31 00 0000 0...

Page 382: ...matches OUMBAR2 3 0 30 28 0002 Outbound Window 2 Function Number Mapping Errors with Outbound Memory Window 2 transactions PCI or Internal Bus are associated with the function number contained in thi...

Page 383: ...t host address space When this register is all zero then a 3DW header is generated on the PCI bus Table 233 Outbound Upper 32 bit Memory Window Translate Value Register 2 OUMWTVR2 Bit Default Descript...

Page 384: ...matches OUMBAR3 3 0 30 28 0002 Outbound Window 3 Function Number Mapping Errors with Outbound Memory Window 3 transactions PCI or Internal Bus are associated with the function number contained in thi...

Page 385: ...it host address space When this register is all zero then a 3DW header is generated on the PCI bus Table 235 Outbound Upper 32 bit Memory Window Translate Value Register 3 OUMWTVR3 Bit Default Descrip...

Page 386: ...te the configuration transaction on the PCI Express Link Table 236 Outbound Configuration Cycle Address Register OCCAR Bit Default Description 31 24 00H Bus Number 23 19 00H Device Number 18 16 000b F...

Page 387: ...ly from the ICPLDQ to the Intel XScale processor and is never actually entered into the data register which does not physically exist The OCCDR is only visible from 81341 and 81342 internal bus addres...

Page 388: ...oint usage and 5 for Root Complex modes Table 238 Outbound Configuration Cycle Function Number OCCFN Bit Default Description 31 03 0000 0000H Reserved 02 00 000 Configuration Cycle Function Number The...

Page 389: ...essages are silently discarded Vendor_Defined message format is shown below in Figure 40 Table 239 Inbound Vendor Defined Message Header Register0 IVMHR0 Bit Default Description 31 24 00H Header Byte...

Page 390: ...he mask bit is set in the ATU Interrupt Mask Register ATUIMR When the mask bit is set then Vendor_Defined Type 0 messages are treated as unsupported requests and Vendor_Defined Type 1 messages are sil...

Page 391: ...e mask bit is set in the ATU Interrupt Mask Register ATUIMR When the mask bit is set then Vendor_Defined Type 0 messages are treated as unsupported requests and Vendor_Defined Type 1 messages are sile...

Page 392: ...sted queues until the status bit is cleared or mask bit is set in the ATU Interrupt Mask Register ATUIMR When the mask bit is set Vendor_Defined Type 0 messages are treated as unsupported requests and...

Page 393: ...ta 1 11 4DW header with data 28 27 10 Type 4 3 10 indicates this is a vendor_defined message Hard wired to 10 26 24 000 Type 2 0 Message Routing The valid encodings are specified below 000 Routed to R...

Page 394: ...Bit Default Description 31 24 00H Requester ID Bus number This value is copied from the Bus number field in the PCISR 23 19 0_0000 Requester ID Device Number This value is copied from the Device numb...

Page 395: ...a write to the OVMPR is still required to initiate the TLP but the data written is ignored Vendor_Defined message format is shown in Figure 40 Table 246 Outbound Vendor Defined Message Header Register...

Page 396: ...message format is shown in Figure 40 Note This register does not physically exist It is simply a write port A read to this register is not claimed by the ATU and causes a data abort This address was...

Page 397: ...emaining details of Initiator ID 27 0 General Device Error GDE This bit is set when an error can not be isolated to a single function and is being logged against all function 26 24 0002 PCI Function N...

Page 398: ...Header is logged 17 0 Receiver Overflow Set when PCI Express receive buffers overflow 16 0 Unexpected Completion As a receiver set whenever a completion is received that does not match the 81341 and 8...

Page 399: ...is masked 19 0 ECRC Check Error Mask When 1 error reporting is masked 18 0 Malformed TLP Error Mask When 1 error reporting is masked 17 0 Receiver Overflow Error Mask When 1 error reporting is masked...

Page 400: ...o ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Write R...

Page 401: ...ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Write...

Page 402: ...ributes Attributes 28 24 20 16 12 8 4 0 31 rv rv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r...

Page 403: ...iates transactions on the internal bus to the MU on behalf of the external PCI agents The MU has four distinct messaging mechanisms Each allows a host processor or external PCI agent and the 81341 and...

Page 404: ...ransactions made to the Messaging Unit registers causes the MU to generate an address error on the internal bus of the 81341 and 81342 Multi word transactions made by an external PCI agent results in...

Page 405: ...nd Interrupt Mask Register Outbound Control and Status Register 2 Doorbell Registers and 0034H 0038H 003CH 0040H Inbound Queue Port Outbound Queue Port reserved 2 Queue Ports 0044H 0048H 004CH 0050H 0...

Page 406: ...4H 4028H 402CH 4034H 4038H 403CH 4040H 4044H 4048H 404CH 4050H 4030H 405CH 4058H 4054H Offset 4004H 4008H 400CH Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head...

Page 407: ...and therefore require ordering The Inbound Post Queue contains PCI writes must be ordered against the inbound write queue of the ATU to allow the data that is represented by the Inbound Post interrupt...

Page 408: ...CI interrupt is recorded in the Outbound Interrupt Status Register The interrupt causes the Outbound Message Interrupt bit to be set in the Outbound Interrupt Status Register This is a Read Clear bit...

Page 409: ...o the Outbound Doorbell Register The interrupt is cleared when an external PCI agent writes a value of 1 to the bits in the Outbound Doorbell Register that are set Writing a value of 0 to any bit does...

Page 410: ...a summary of the queues The two outbound queues allow the Intel XScale processor to post outbound messages in one queue and to receive free messages returning from the host processor The Intel XScale...

Page 411: ...e head and tail pointers are incremented by either the Intel XScale processor or the Messaging Unit hardware Which unit maintains the pointer is determined by the writer of the queue More details abou...

Page 412: ...esses of each queue is based on the Queue Base Address and the Queue Size field Table 261 shows an example of how the circular queues should be set up based on the Intelligent I O I2O Architecture Spe...

Page 413: ...cremented by Outbound Post Incremented by Incremented by Inbound Post Incremented by Incremented Inbound Free External PCI Agent Read Write Read Write Outbound Inbound Low Address Memory External PCI...

Page 414: ...te accesses to the Inbound Free Queue The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register When the internal bus read access occurs...

Page 415: ...ust process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt Once cleared an interrupt is NOT generated when the head and tail pointers remain unequ...

Page 416: ...om the prefetch register The prefetch mechanism loads a value of 1 FFFF FFFFH into the prefetch register when the head and tail pointers are equal and the queue is empty In order to update the prefetc...

Page 417: ...ster The interrupt is cleared when the Outbound Free Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers The interrupt can be masked by the Inbound Interrupt Mask Regis...

Page 418: ...ost Queue and Outbound Free Queue Tail Pointers are only managed by software respectively using the Inbound Post Tail Pointer Register IPTPR and Outbound Free Tail Pointer Register OFTPR during normal...

Page 419: ...ers allow the index registers to be placed in any 8 KByte space of the Host I O Interface Address Translation window The address of the first write access is stored in the Index Address Register This...

Page 420: ...it like the ATU encounters error conditions on the host I O interface as well as the internal bus interface As a host I O interface target all host I O interface errors are captured and recorded in th...

Page 421: ...ch MSI capable device is allowed Then software writes the Message Address Registers and the Message Upper Address Registers when Message Address is above the 4G address boundary18 and the Message Data...

Page 422: ...ffset Register and MSI X Pending Bits Array Register to determine the locations these structures After gathering this data from all of the MSI X capable devices in the system the configuration softwar...

Page 423: ...sult in the assertion of the P_INTx output pin However all the P_INT A D pins are functional for steering of interrupts from other PCI devices that may not be MSI capable MSI X Table and Pending Bits...

Page 424: ...level triggered the interrupt service routine does not drop out of the service routine until the interrupt signal is deasserted This insures that an interrupt is not missed MSI interrupts are inherent...

Page 425: ...nterrupt Status Register Inbound Interrupt Mask Register Outbound Doorbell Register Outbound Interrupt Status Register Outbound Interrupt Mask Register Inbound Reset Control and Status Register Outbou...

Page 426: ...n 4 9 14 Inbound Free Head Pointer Register IFHPR on page 439 4064H Section 4 9 15 Inbound Free Tail Pointer Register IFTPR on page 439 4068H Section 4 9 16 Inbound Post Head Pointer Register IPHPR on...

Page 427: ...e Intel XScale processor may be generated PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 428: ...register can only be set by an external Host I O Interface agent and can only be cleared by the Intel XScale processor Table 267 Inbound Doorbell Register IDR Bit Default Description 31 02 Error Inter...

Page 429: ...und Free Queue Full Interrupt This bit is set when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full An Error interrupt is generated for this condition 04 02 Inbou...

Page 430: ...is bit masks the interrupt generated by the MU hardware when an Index Register has been written after a Host I O Interface transaction 05 02 Outbound Free Queue Full Interrupt Mask When set this bit m...

Page 431: ...C When set this bit causes the P_INTC signal to be asserted or a Message signaled Interrupt is generated when enabled When this bit is cleared the P_INTC signal is deasserted 29 02 PCI Interrupt B Wh...

Page 432: ...the interrupt the PCI Interrupt C bit must be cleared 05 02 PCI Interrupt B This bit is set when the PCI Interrupt B bit is set in the Outbound Doorbell Register To clear this bit and the interrupt th...

Page 433: ...PCI Interrupt C signal when the PCI Interrupt C bit in the in the Outbound Doorbell Register is set 05 02 PCI Interrupt B Mask When set this bit masks the PCI Interrupt B signal when the PCI Interrupt...

Page 434: ...tions of the RCSR register Table 273 Inbound Reset Control and Status Register IRCSR Bit Default Description 31 02 00000000H Reserved 01 02 Coordinated Reset CR This bit is valid when the 81341 and 81...

Page 435: ...col is not implemented this bit is always zero Note The state of this bit is saved in the Reset Cause Status Register RCSR when an internal bus reset occurs Refer to the Exception Initiator and Boot S...

Page 436: ...e 275 MSI Inbound Message Register MIMR Bit Default Description 31 16 0000H Reserved 15 02 Core Select Bit This bit is used to select the Intel XScale processor which is the target of the MSI Interrup...

Page 437: ...of the 36 bit QBR Local memory is 36 bit addressable 15 06 000000H Reserved 05 01 000012 Circular Queue Size This field determines the size of each Circular Queue All four queues are the same size 000...

Page 438: ...g to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register Warning The QBAR must designate a range allocated to the 81341 and 8...

Page 439: ...Address Local memory address of the circular queues 19 02 0000H 002 Inbound Free Head Pointer Local memory offset of the head pointer for the Inbound Free Queue 01 00 002 Reserved PCI IOP Attributes...

Page 440: ...al memory address of the circular queues 19 02 0000H 002 Inbound Post Head Pointer Local memory offset of the head pointer for the Inbound Post Queue 01 00 002 Reserved PCI IOP Attributes Attributes 2...

Page 441: ...ueue Base Address Local memory address of the circular queues 19 02 0000H 002 Outbound Free Head Pointer Local memory offset of the head pointer for the Outbound Free Queue 01 00 002 Reserved PCI IOP...

Page 442: ...cal memory address of the circular queues 19 02 0000H 002 Outbound Post Head Pointer Local memory offset of the head pointer for the Outbound Post Queue 01 00 002 Reserved PCI IOP Attributes Attribute...

Page 443: ...least recently accessed is computed by adding the Index Address Register to the Inbound ATU Translate Value Register Table 286 Index Address Register IAR Bit Default Description 31 12 000000H Reserve...

Page 444: ...by the MU and not by the DDR MCU Overlapping the MU space onto the DDR MCU space is required when the Index registers are required because the Index registers are implemented using the DDR Memory Note...

Page 445: ...he default values programmed in the Inbound ATU Translate Value Register 0 IATVR0 Inbound ATU Upper Translate Value Register 0 IAUTVR0 This allows the MU registers to be mapped in the first 8 KByte of...

Page 446: ...is field contains the lower 30 bits of the MSI X Message Address 01 00 002 Reserved PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 447: ...age Upper Address This field contains the upper 32 bits of the MSI X Message Address PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r...

Page 448: ...ata This field contains the message data for this Table entry PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 449: ...Message Vector Control This bit when set prohibits the sending an MSI X message using this entry PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv...

Page 450: ...rray Register M_MPBAR Bit Default Description 31 08 0000 000H Reserved 07 00 000000002 Pending Bits Array Any bit that is set indicates that the associated MSI X message is scheduled to be sent When a...

Page 451: ...the Peripheral Registers Chapter for the default internal bus address This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint Table 295 MSI Next...

Page 452: ...the 81341 and 81342 is capable of generating a 64 bit message address 6 4 0002 Multiple Message Enable System software writes to this field to indicate the number of messages allocated to the 81341 an...

Page 453: ...ce of the Address Translation Unit that is setup as an endpoint Table 297 Message Address Register Message_Address Bit Default Description 31 2 00000000H Message Address DWORD aligned Message Address...

Page 454: ...Registers Chapter for the default internal bus address This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint Table 298 Message Upper Address Re...

Page 455: ...ble 299 Message Data Register Message_Data Bit Default Description 15 00 0000H Message Data System software specifies a 16 bit value to be transferred during the data phase of an MSI write transaction...

Page 456: ...Addendum to the PCI Local Bus Specification Revision 2 0 Note Refer to the Peripheral Registers Chapter for the default internal bus address This register is part of the configuration space of the Add...

Page 457: ...pter for the default internal bus address This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint Table 301 MSI X Next Item Pointer Register MSI X...

Page 458: ...set all the vectors in the MSI X Table are globally masked regardless of the per vector Mask Bit states in the Vector Control Register of the MSI X Table entries 13 11 0002 Reserved 10 00 00000000000...

Page 459: ...KByte of address space and must overlap the address space defined by the ATU Value and the ATU Limit registers Equation MSI X Table Offset 31 13 ATU Limit_Register 31 0 MU_Bar 31 0 13 Note The defaul...

Page 460: ...ccupies 8 KByte of address space and must overlap the address space defined by the ATU Value and the ATU Limit registers Equation MSI X Table Offset 31 13 ATU Limit_Register 31 0 MU_Bar 31 0 13 Note T...

Page 461: ...nerated Table 305 MU MSI X Control Register X MMCRx Bit Default Description 31 01 0000 0000H Reserved 00 02 MU MSI X Single Message Vector This bit when set causes only a single MSI X Message to be ge...

Page 462: ...egisters before setting the Circular Queue Enable bit Table 306 Inbound MSI Interrupt Pending Registers IMIPR 0 3 Bit Default Description 31 00 0000 0000H Inbound MSI Pending Interrupts Each bit refle...

Page 463: ...st memory blocks provides a hardware assist to the iSCSI application by calculating CRC 32C on a single data stream and performs memory block fills ADMA is fully programmable from 81341 and 81342 and...

Page 464: ...or a single strip RAID 6 write the dual XOR operation generates the Horizontal and Diagonal Parity results using new data old data old horizontal parity and old diagonal parity A GF Multiply calculati...

Page 465: ...writing the source addresses destination address number of bytes to transfer and various control information into a chain descriptor Chain descriptors are described in detail in Section 5 3 ADMA Descr...

Page 466: ...P Q transfer The source and destination addresses are specified through the chain descriptors resident in 81341 and 81342 local memory There are four types of chain descriptors Basic Full Dual XOR an...

Page 467: ...e Memory Block Fill operation To perform a transfer one or more chain descriptors must first be written to memory Figure 48 shows the format of an individual basic chain descriptor Every basic descrip...

Page 468: ...Register The fourth word contains the 24 bit Byte Count value This value specifies the number of bytes of data in the current chain descriptor Also the upper byte of this word is the Transfer Status...

Page 469: ...red to be aligned on a 32 byte address boundary Figure 49 Full Chain Descriptor Format Word 8 Word 9 Word 11 Word 10 Word 21 Word 20 Word 0 Word 7 Word 13 Word 12 Word 15 Word 14 Word 17 Word 16 Word...

Page 470: ...is value is loaded into the Source Lower Address Register 5 The eighteenth word is the upper 32 bit source address for source 5 of the XOR transfer operation This value is loaded into the Source Upper...

Page 471: ...XOR transfer operation This value is loaded into the Source Lower Address Register 13 The thirty fourth word is the upper 32 bit source address for source 13 of the XOR transfer operation This value...

Page 472: ...to be aligned on a 32 byte address boundary While a minimum of eight words are required a maximum of 38 words may be used to perform the P Q function on up to 16 source data streams Note The minimum s...

Page 473: ...dress Lower Word 31 Word 30 Source 13 Address Lower Word 33 Word 32 Source 15 Address Lower Word 37 Word 36 DMLT13 Source 13 Address Upper DMLT12 Source 12 Address Upper DMLT11 Source 11 Address Upper...

Page 474: ...ation This value is loaded into the Source Upper Address Register 0 Ninth word is lower 32 bit source address for source 1 of the P Q transfer operation This value is loaded into the Source Lower Addr...

Page 475: ...P Q transfer operation This value is loaded into the Source Upper Address Register 10 Twenty ninth word is lower 32 bit source address for source 11 of the P Q transfer operation This value is loaded...

Page 476: ...ary All 16 words are required Note Bits 3 down to 0 of the Horizontal Destination Address Word 4 and 5 and the Diagonal Destination Address Word 14 and 15 must be programmed to the same four bit value...

Page 477: ...MA uses this value for the upper 32 bits of the Horizontal destination address for the Dual XOR transfer operation This value is loaded into the Destination Upper Address Register Seventh word is lowe...

Page 478: ...ss Word 4 and 5 are programmed to the same four bit value Furthermore the hardware requires this even if the P Transfer Disable bit is set to disable P transfer to the P_Destination Address For exampl...

Page 479: ...uses this value for the upper 32 bits of the P destination address for the P Q Update Transfer operation This value is loaded into the Destination Upper Address Register Seventh word is the P Q Update...

Page 480: ...s in the chain descriptor This address logically links the chain descriptors together This allows the application to build a list of transfers which may not require the processor until all transfers a...

Page 481: ...ear 5 The ADMA starts the ADMA operation by reading the chain descriptor at the address contained in ANDAR The ADMA loads the chain descriptor values into the ADAR and begins data transfer The ADMA De...

Page 482: ...is set an interrupt is generated to the Intel XScale processor This interrupt is for synchronization purposes The ADMA sets the End Of Transfer Interrupt flag in the ADMA Channel Status Register ACSR...

Page 483: ...r nA generated an interrupt to signify the end of the chain has been reached The right column in Figure 54 shows an example where the interrupt was generated only on the last descriptor signifying the...

Page 484: ...e ADMA examines the Chain Resume bit of the ACCR when the unit is idle or upon completion of a chain of transfers When this bit is set the ADMA re reads the Next Descriptor Address of the current chai...

Page 485: ...AM as the transfer destination 00 10 while the remaining two buffers are used when either the Internal Bus or the Host I O interface is selected as the transfer destination 01 11 These queues temporar...

Page 486: ...eld the CRC Value is read written from the Internal Bus using the CRC Address contained in the Basic Descriptor and the upper CRC Address contained in the ACCR When Data Transfer during a CRC operatio...

Page 487: ...sses unaligned 5 6 1 64 bit Unaligned Data Transfers Figure 55 illustrates an ADMA transfer between unaligned 64 bit source and destination addresses Figure 55 Optimization of an Unaligned ADMA Transf...

Page 488: ...10 9 8 15 14 13 12 16 Address MSB MSB LSB A000 0200H A000 0204H A000 0208H A000 020CH A000 020CH 32 Bit Source Bus PCI Bus 64 bit Destination Bus Internal Bus Programmed Values Bus Operation 5 4 3 2 1...

Page 489: ...The updated Q check data stream is comprised of the XOR of the same two source data streams that have been Galois field multiplied and a Q check data stream on a per byte basis All four data streams...

Page 490: ...ch of the seven ADMA operations are supported in each of the 3 ADMA Channels Table 309 Supported ADMA Operations per ADMA Channela a Y Supported Operation N Operation Not Supported ADMA Operation ADMA...

Page 491: ...hat as data is read from local memory the boolean unit executes the XOR operation on incoming data Figure 57 The Bit wise XOR Algorithm 0A0000400H Block 1 MSB LSB 0A0000800H 0A0000C00H 0A0001000H bitw...

Page 492: ...002US Figure 58 Hardware Assist XOR Unit New Data XORed Data bytes 1 8 bytes 9 16 bytes 1021 1024 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Block 1 Byte 1024 Byte 1024 Byte 1024 Byte 1024 Byte 1024 Block 1 B...

Page 493: ...in the queue and the first eight bytes of data just read from SAR1 bytes 1 8 4 XOR ed result is transferred to the XOR store queue and stored in the first eight bytes bytes 1 8 overwriting previously...

Page 494: ...d applies the GF Multiply function to the incoming source data followed by the XOR operation to generate Q Only a single descriptor is required and generates both check values Each descriptor is proce...

Page 495: ...e5 ac 73 f3 a7 57 8 07 70 c0 f7 8c 80 63 0d 67 4a de ed 31 c5 fe 18 9 e3 a5 99 77 26 b8 b4 7c 11 44 92 d9 23 20 89 2e a 37 3f d1 5b 95 bc cf cd 90 87 97 b2 dc fc be 61 b f2 56 d3 ab 14 2a 5d 9e 84 3c...

Page 496: ...fficient equal to 1 The Q generation coefficients G 0 G 1 G 2 G N 1 are computed from the Vandermond matrix based on the array data disk count N The P and Q check values are computed by the ADMA using...

Page 497: ...a transfer The algorithm is implemented such that as data is read from local memory the boolean unit executes the XOR operation on incoming data Figure 63 The Bit wise Dual XOR Algorithm 0 A000 0400H...

Page 498: ...002US Figure 64 Hardware Assist XOR Unit New Data XORed Data bytes 1 8 bytes 9 16 bytes 1021 1024 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Block 1 Byte 1024 Byte 1024 Byte 1024 Byte 1024 Byte 1024 Block 1 B...

Page 499: ...iously stored data 5 The Application DMA transfers the next eight bytes of data bytes 9 16 from address pointed at by the Second Source Address Register SAR1 6 The XOR unit performs the bit wise XOR a...

Page 500: ...kept in the ADMA P and Q result buffers before being written back to local memory The source data is located at addresses 0 A000 0400H 0 A000 0800H 0 A000 0C00H and 0 A000 1000H respectively All data...

Page 501: ...e byte 1 byte 8 1024 bytes bytes 1 8 bytes 1 8 bytes 1 8 bytes 1 8 1024 bytes P_Source 0000 0000 A000 0C00H Q_Destination 0 B000 0400H Q_Source 0100 0000 A000 1000H SAR1 0000 0000 A000 0800H SAR0 0000...

Page 502: ...e fourth word of the descriptor ABCR or signals an interrupt to the Intel XScale processor and suspend ADMA operation Figure 66 An Example of Zero Result Buffer Check A000 0400H Block 1 MSB LSB A000 0...

Page 503: ...processor and suspend ADMA operation This operation can perform a consistency verification of the P and Q check data blocks associated with up to 14 data blocks Even though there are 16 Source Addres...

Page 504: ...1 8 bytes 1 8 1024 bytes Block 2 Control Register Values Local Memory GF Multiply GF Multiply GF Multiply DMLT1 01 DMLT2 02 DMLT3 04 Block 3 1024 bytes 1024 bytes P Block 4 bytes 1 8 1024 bytes Q Bloc...

Page 505: ...y block fill operations are controlled by chain descriptors located in memory Figure 68 illustrates a Block Fill Operation to an arbitrary destination address Note The Destination Address is used to d...

Page 506: ...forms the following steps in addition to the Data Transfer Note When Word 3 Byte Count is set to 0 then the CRC seed value is not affected and the ADMA advances to the next descriptor 1 Prior to the s...

Page 507: ...her PDU e g CRC Address is different For example Descriptor 3 in Table 310 on page 507 Table 310 Multiple Descriptor Usage for CRC Calculation of a 3 Fragment PDU Order of Descriptors in Chain CRC Ena...

Page 508: ...on page 508 The initial seed for this operation is required to be FFFF FFFFh which is equivalent to the initial value of the CRC internal register in Figure 70 Figure 69 CRC 32C Generator Polynomial F...

Page 509: ...ADAR and load ANDAR ABORT 0 Read Descriptor at ANDAR ANDAR 0 XOR Transfer Memory Block Fill Parity Checking Transfer Complete I B e r r o r ANDAR 0 IDLE STATE Read Descriptor State READ NAD STATE ADM...

Page 510: ...The internal bus arbitration logic determines which internal bus master has access to the 81341 and 81342 internal bus The Application DMA has an independent Bus Request Grant signal pair to the inter...

Page 511: ...in Figure 73 describes the pseudo code for initiating an XOR operation with the ADMA for four sources ADMA initialization Start Transfer Suspend ADMA Figure 72 Pseudo Code Application DMA Initializati...

Page 512: ...des the ability to suspend the current state without losing status information The ADMA resumes without requiring application software to save the current configuration Figure 74 describes pseudo code...

Page 513: ...DMA internal bus interface checks the address parity during the address request phase asserts the internal bus error signal when it detects an address parity error The address parity error is logged b...

Page 514: ...bus interface generates and drives even parity on the internal address bus for either a read or a write request When the target of the ADMA request detects an address parity error the target discards...

Page 515: ...tes that are used for the address and data parity calculation The parity bits are calculated by bit XORing the data bits shown in Table 311 As an example the parity calculation for the lowest order by...

Page 516: ...ss parity bits are checked by first calculating the parity bits on the incoming address bytes shown in Table 311 and verifying the results against the corresponding incoming address parity signals As...

Page 517: ...Table 312 and verifying the results against the corresponding incoming data parity bits As an example the parity calculation for the lowest order byte of the data bus D 7 0 is carried as follows Equat...

Page 518: ...I n t e r f a c e P a r i t y E r r o r I n t e r n a l B u s M a s t e r A b o r t i n t e r n a l B u s T a r g e t A b o r t M C U P o r t A b o r t Z e r o R e s u l t B u f f e r E r r o r Z e r...

Page 519: ...r after an error condition It is the responsibility of the application software to reconfigure the ADMA to complete any remaining transfers Note Target aborts during ADMA reads result either from mult...

Page 520: ...e 0_FFD8_0404H 0_FFD8_0000H 0_0400H 004H Table 314 ATU Internal Bus Memory Mapped Register Range Offsets ADMA Unit ADMA Address Offset Relative to PMMRBAR ADMA0 0 0000H ADMA1 0 0200H ADMA2 0 0400H Tab...

Page 521: ...or chain to be located within a single 4 Gbyte address range defined by this register 19 02 Endian Mode Selector This bit selects the Host vs Local Memory Endian mode This is used by the ADMA when the...

Page 522: ...iptor Address in chain descriptor Internal Bus Errors When the Status Write Back Enable bit 12 of the DC is cleared Zero Result Buffer Error User Defined Tag Verification Error or Data Guard Verificat...

Page 523: ...ero Result Buffer Check this represents a non zero result on the P Zero Result Buffer check 01 02 This bit is set when a P Q Zero Result Buffer error is detected on the Q Zero Result Buffer check when...

Page 524: ...04 00 000002 Reserved Host IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro...

Page 525: ...in the ACCR and the ADMA Active bit in the ACSR must both be clear prior to writing the ANDAR Writing a value to this register while the ADMA is active may result in undefined behavior Table 320 ADMA...

Page 526: ...treams see Section 5 7 3 XOR Operation with P Q RAID 6 on page 494 and transfer them to the P_Destination and Q_Destination respectively 17 02 Dual XOR Enable When set the ADMA interprets this descrip...

Page 527: ...by the XOR or Zero Result Buffer operations 0000 SAR0 1 Source Data Transfer CRC Memory Block Fill 0001 SAR1 0 2 Sources XOR Zero Result Check operation with 2 sources 0010 SAR2 0 3 Sources XOR Zero...

Page 528: ...ogrammed in the descriptor Note When a Transfer Direction using the Internal Bus or Local Memory is selected the programmed range of addresses Source Destination is direct mapped from the ADMA onto th...

Page 529: ...Destination All chain descriptors are aligned on an eight 32 bit word boundary Table 322 CRC Address Memory Block Fill Data Q_Destination Register x CARMDQx Bit Default Description 31 00 0000 0000H CR...

Page 530: ...ult Buffer Error This bit is set when the bit wise XOR computed across the data blocks specified by the SARx registers results in the detection of a non zero result i e an invalid parity block For a P...

Page 531: ...ed in the CRC Address Memory Block Fill Data Q_Destination Register x CARMDQx on page 529 For a P Q Transfer this register is used for the lower 32 bits of the P_Destination This register is read only...

Page 532: ...l XOR chain descriptor is read from memory Note When the Transfer Direction field bits 2 1 of the ADCR maps the destination address to the Host I O interface this register represents bits 63 32 of the...

Page 533: ...lock SLAR2_x Lower 32 bit address of the Horizontal source data block SLAR3_x Lower 32 bit address of the Diagonal source data block SLAR4_x Lower 32 bit address of the Diagonal destination block For...

Page 534: ...y Address lower 32 bit Local memory source address Host IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro n...

Page 535: ...ations the following SUAR0 15_x registers have been redefined SUAR0_x Upper 32 bit address of the first source data block SUAR1_x Upper 32 bit address of the second source data block SUAR2_x Upper 32...

Page 536: ...he descriptor formats Table 327 Source Upper Address Register 0 15_x SUAR0 15_x Bit Default Description 31 24 00H Data Multiplier DMLT0 15 In a P Q operation this value is the 8 bit Galois field multi...

Page 537: ...al busses on 81341 and 81342 and therefore there are two system controllers implemented one for the North Internal Bus and one for the South Internal Bus The north internal bus SC controls the two Int...

Page 538: ...data bus and implements an arbitration algorithm to generate data bus grant to grant the data bus to a particular requesting agent The SC frames the data transactions and therefore initiates the data...

Page 539: ...ister also provides an enable bit which must be set by software and is reset by hardware This provides a way of injecting an error only once a one shot process For example error is injected only durin...

Page 540: ...making address requests In addition these same Initiator IDs can be used when injecting data parity error when these initiators are pushing data during writes Table 330 Data Parity Testing Completer...

Page 541: ...orth internal bus from the south internal bus are referred to as inbound transactions Figure 77 Intel 81341 and 81342 I O Processors Block Diagram External PCI X or PCI E Intel 81342 I O Processor 16...

Page 542: ...interface Both the north and south internal busses on 81341 and 81342 support the same bus protocol The internal bus operates by performing split transactions on both read and write address requests E...

Page 543: ...he address is aligned on a 32 byte boundary In other words for a non 32 byte aligned address the sum of the non aligned address and byte count has to be less than the next 32 byte aligned address boun...

Page 544: ...Limit Register BWLR Transactions on the south internal bus that target this memory window are claimed and forwarded to the north internal bus The South Bridge Interface also claims transactions that...

Page 545: ...uests targeting only the north interface of the Bridge For example outbound write requests from the north internal bus to the south internal bus Although the bridge must allow write requests to pass r...

Page 546: ...bus to the south internal bus as either a read completion or write request the bridge generates data parity as the data enters the north bridge interface The data and its parity are stored in the inte...

Page 547: ...rror by performing a target abort during the read completion Address Request Error on the north internal bus interface This condition may happen when a target on the north internal bus detected an err...

Page 548: ...e address request For example the target may indicate that the byte count is out of range or the target detected an address parity error For a write request the bridge logs the address request error c...

Page 549: ...l Bus Arbitration Control Register provides controls for both the North and South Internal address busses The south internal bus address and data test registers are used to force address or data parit...

Page 550: ...the south interface The Bridge Error Status register indicates the type of error that was encountered by the bridge on either the north or south interfaces The Bridge Error Address and Error Upper Add...

Page 551: ...rol the address initiators on the north internal address bus and bits 31 16 control the address initiators on the south internal address bus Warning Since the internal address arbiter parks on an agen...

Page 552: ...t granted the south internal address bus when this bit is set 0 Enabled 1 Disabled 15 03 000H Reserved 02 02 Reserved 01 02 XSC coreID1 control this bit controls coreID1 The Intel XScale processor wit...

Page 553: ...escription 31 21 000H Reserved 20 16 000002 Address Parity Mask bits Each bit of the generated address parity is XORed with the appropriate bits in this mask field before the parity bits are driven on...

Page 554: ...scription 31 16 00002 Data Parity Mask bits Each bit of the generated data parity is XORed with the appropriate bits in this mask field before the parity bits are driven on the south internal bus Bit1...

Page 555: ...tarting address after reset is 0 FFD8 0000H Table 336 Peripheral Memory Mapped Register Base Address Register PMMRBAR Bit Default Description 31 15 0000 1111 1111 1101 12 PMMR Base Address These bits...

Page 556: ...hrough bit 31 of the base address from the Bridge Base Address Register BBAR are relevant to the Bridge when decoding Memory Window Warning Care must be exercised when modifying the Bridge Base BBAR a...

Page 557: ...arity of the memory block size For instance when a 64 Kbyte memory window size is selected the base address needs to be 64 Kbyte address aligned i e bits 15 12 of the base address are required to be 0...

Page 558: ...Bridge Window Upper Base Address Register BWUBAR Bit Default Description 31 04 0000 000H Reserved 03 00 0H Bridge Upper Memory Window Base Address These bits are the upper 4 bits of the 36 bit base ad...

Page 559: ...le 340 Bridge Limit Register BWLR Bit Default Description 31 12 FFF0 0H Bridge Memory Window Limit This value determines the memory range required for the Bridge Memory Window Defaults to a 1MB Memory...

Page 560: ...uth Internal Bus Error is detected When cleared an interrupt to the Intel XScale processor is not signaled when a South Internal Bus Address Error is detected Note This enable applies to all error typ...

Page 561: ...f the errors as there is only one set of log registers 01 02 Error N Detected Indicates that the Bridge detected an error on either the north or south internal bus interface while BECSR 0 was set 0 No...

Page 562: ...address of the request that resulted in an error PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na...

Page 563: ...o a high bandwidth and reliable memory subsystem The DDR2 SDRAM interface consists of a 64 bit wide data path to support up to 4 3 GBytes s throughput An 8 bit Error Correction Code ECC across each 64...

Page 564: ...2 Mbit and 1 Gbit and 2 Gbit DDR II SDRAM devices 512 Mbit DDR 2 SDRAM devices support four internal banks whereas 1 Gbit and 2 Gbit DDR 2 SDRAM devices support eight internal banks An internal bank i...

Page 565: ...he memory controller logically comprises the blocks illustrated in Figure 78 The memory controller is a multi ported unit supporting inbound paths from the north internal bus the south internal bus th...

Page 566: ...South Internal Bus Port The South IB Port provides the connection to the DDR SDRAM from the South IB Bus Peripheral unit transactions targeting the DDR SDRAM are claimed by this port For example the...

Page 567: ...h the Primary Memory Window The Secondary Memory Window is setup using the Secondary SDRAM Base Register SSDBR and the DDR SDRAM Bank Size Register SBSR 7 3 1 2 2 Memory Mapped Register Space The DMCU...

Page 568: ...tus registers indicate the current DMCU status 7 3 1 5 Refresh Counter The Refresh Counter block keeps track of when the DDR SDRAM devices need to be refreshed The refresh interval is programmed in th...

Page 569: ...four internal banks which therefore accounts for a total of eight pages when both memory banks are implemented This block keeps track of open pages and determines when the transactions hit an open pag...

Page 570: ...Transaction Count Register DMPTCR on page 648 These registers enable the DMCU to be tuned for optimal design performance 7 3 2 1 DMCU Port Priority The Memory controller for the 81341 and 81342 has si...

Page 571: ...requests addressing the DDR SDRAM Coherency between the north IB port south IB port and the other ports are maintained by the DMCU as described in DMCU Port Coherency below 7 3 2 5 South Internal Bus...

Page 572: ...data bus width memory implementations with and without ECC The data bus width is controlled by the DDR SDRAM Control Register In addition a 64 bit data bus width DDR SDRAM implementation is configure...

Page 573: ...de asserted data is latched on DQ 63 0 and CB 7 0 Burst counters within DDR SDRAM device are not incremented De asserting this signal places DDR SDRAM in self refresh mode For normal operation CKE 1...

Page 574: ...tel 81341 and 81342 I O Processors Dual Bank DDR SDRAM Memory Subsystem Intel 81341 and 81342 I O Processors DQS 8 0 DQS 8 0 CB 7 0 RAS CAS WE MA 13 0 BA 2 0 DM 8 0 CKE0 CKE1 CS0 CS1 DQ 63 00 M_CK 2 0...

Page 575: ...ddress Translation for 512 Mbit x8 and 1 Gbit x8 Devices SDCR0 6 cleared MA 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row A 26 A 25 A 24 A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 Column V1...

Page 576: ...ls 2 For the Leaf Selects see Table 358 Table 353 DDR2 SDRAM Address Translation for 512 Mbit x8 Device SDCR0 6 set MA 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row A 28 A 27 A 26 A 25 A 24 A 23 A 22 A...

Page 577: ...fashion during burst cycle Random bursting means that the address issued with every new command to the DDR SDRAM can be any address in a currently active page Note The DMCU only supports Sequential B...

Page 578: ...f Select Total Memory Sizea a Table indicates 64 bit wide memory subsystem sizes For 32 bit wide memory the memory subsystem size would be half of that indicated Row Column BA 2 BA 1 BA 0 512 Mbit 64M...

Page 579: ...rocessing performance a 32 bit region can be defined within Bank 0 with the DDR SDRAM 32 bit Region Size Register S32SR Note The Base Address registers SDBR and SDUBR must be programmed to align on bo...

Page 580: ...alid region reflects the other half of the 64 bit DDR SDRAM which is not used in the 32 bit region Transactions which address this region results in an error and interrupt to the Intel XScale microarc...

Page 581: ...est 4 GByte of the address space Note that the secondary memory window may be smaller than the primary memory window and that the secondary memory window must never be larger than the total SDRAM size...

Page 582: ...o the Primary Memory Window first as if the Secondary Memory Window does not exist Only after setting up the Primary Memory Window the Programmer can setup and enable the Secondary Memory Window as ex...

Page 583: ...DDR Memory Controller Interrupt Status Register DMCISR on page 647 Since the DMCU maintains memory coherency as described in section Section 7 3 2 7 DMCU Port Coherency on page 571 the upper four bit...

Page 584: ...63 shows correct programming values for 32 bit DDR SDRAM Size Register The maximum size of the 32 bit region is one half of Bank 0 size all banks are same size or 512 MBytes whichever is smaller Table...

Page 585: ...bank is 512 MBytes yielding in a total memory of 1 GBytes 2 512 MB The user wants the DDR memory space to start at A C000 0000H There is no 32 bit memory region and no secondary window The memory spac...

Page 586: ...ry only The smallest DDR2 size that can be supported is 128 M Bytes as dictated by the DDR2 technology The user wants the DDR memory space to start at B F800 0000H The memory space summary is The regi...

Page 587: ...y space to start at A 0000 0000H The user wants a 2 GByte secondary window starting at 0 0000 0000H Note that the secondary memory window overlaps the primary memory window and starts at the bottom of...

Page 588: ...he DMCU does not support switching between 32 bit data bus width and 64 bit data bus width The data bus width is selected by bit 2 of the SDCR0 see Section 7 8 2 SDRAM Control Register 0 SDCR0 on page...

Page 589: ...512 Mbit DDR2 devices the DMCU keeps four pages per bank 8 maximum open simultaneously And for 1 Gbit and 2 Gbit DDR2 devices the DMCU keeps eight pages per bank 16 maximum open simultaneously For 512...

Page 590: ...eaf4 Bank1 Leaf5 Bank1 Leaf6 Bank1 Leaf7 S C E 1 0 S B A 2 0 Open Page Address0 Valid Open Page Address1 Valid Open Page Address2 Valid Open Page Address3 Valid Open Page Address4 Valid Open Page Addr...

Page 591: ...pointed to by CS 1 0 and BA 2 0 by issuing a precharge command The DMCU opens the current page with a row activate command and the transaction completes with a read or write command When the DMCU open...

Page 592: ...af 5 Page 0 Bank 0 Leaf 6 Page 1 Bank 0 Leaf 7 Page 2 Bank 1 Leaf 0 Page 3 Bank 1 Leaf 1 Page 0 Bank 1 Leaf 2 Page 2 Bank 1 Leaf 3 Page 1 Bank 1 Leaf 4 Page 3 Bank 1 Leaf 5 Page 0 Bank 1 Leaf 6 Page 2...

Page 593: ...A 1 0 Selc c Selects which mode register is programmed 002 selects Mode Register 012 selects Extended Mode Register 102 selects Extended Mode Register 2 and 112 selects Extended Mode Register 3 Load t...

Page 594: ...serts CKE 1 0 for a minimum of 200 us after supply voltage reaches the desired level Asserting P_RST achieves this state 4 Software disables the refresh counter by setting the RFR to zero 5 Software i...

Page 595: ...two auto refresh cycles accomplished by setting SDIR to 0000_0010H then ensure at least Trfc cycles between each auto refresh command 13 After the second auto refresh cycle software must wait Trfc cy...

Page 596: ...0 0 X X X 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 X X X X 0002 9900H MRS Command tWR 3 Do NOT reset DLL Set CAS Latency 3 Set Burst Type Sequential Set Burst Length 4 0 0 X X X X 0 0 0 X X X 0 0 1 0 0 0 0 1 1...

Page 597: ...th L L L X X X X MRS Command tWR 4 Do NOT reset DLL Set CAS Latency 5 Set Burst Type Sequential Set Burst Length 4 0 0 X X X X 0 0 0 X X X 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 X X X X 0003 2900H EMRSi Para...

Page 598: ...d Output enabled RDQS Enable Yes DQS Enable enable OCD Program exit RTT 150 ohm Additive latency 000b disableDLL 0 0 X X X X 0 0 1 X X X 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 X X X X 0080 2080H a MRS Comman...

Page 599: ...Select 12 OUT Output Buffer Enable Disable 11 RDQS RDQS Enable 10 DQS DQS Enable 09 07 OCD Program OCD Operation 06 RTT RTT 05 03 Posted CAS Posted CAS Additive latency AL 02 RTT RTT 01 ODS Out Drive...

Page 600: ...ay attempt to read memory locations beyond the specified word s In this case the DMCU reports an ECC error even though software did not specifically request the un initialized data Figure 88 DDR SDRAM...

Page 601: ...ity in the type of DDR device that is selected in addition to de coupling the hardware to any frequency dependencies See Section 7 8 2 SDRAM Control Register 0 SDCR0 on page 628 and Section 7 8 3 SDRA...

Page 602: ...se see the JEDEC specification for the timing parameters specific to the DDR device that is to be implemented in the system Note Burst Length BL is fixed at four for 81341 and 81342 Figure 89 DMCU Act...

Page 603: ...e hit A read that misses the open pages encounters a miss penalty because the currently open page needs to be closed before the read can be issued to the new page Refer to Section 7 3 3 5 Page Hit Mis...

Page 604: ...be closed before the write can be issued to the new page Refer to Section 7 3 3 5 Page Hit Miss Determination on page 589 for the paging algorithm details When a page hit occurs steps 2 3 are skipped...

Page 605: ...ddress of the next transaction to be issued before the current transaction s data transfer is completed by the DDR SDRAM devices These optimizations are illustrated in Figure 90 for random write memor...

Page 606: ...ated DDR SDRAM banks The DDR SDRAM Control Block resets the page register valid bits The DDR SDRAM Control Block issues an auto refresh command to DDR SDRAM bank 0 This command affects all internal le...

Page 607: ...40 bit wide memory subsystem During DDR SDRAM read cycles the DDR SDRAM Control Block detects single bit errors and corrects the data prior to returning the data to the respective memory transaction q...

Page 608: ...thm for a write transaction is if data to write is 64 bits wide Generate the ECC_with the G matrix Write the new data and ECC else Partial Write Read entire 64 bit data word from memory Merge the new...

Page 609: ...3 2 CB0 X X X X X X X X X X X X X X X X CB1 X X X X X X X X X X X X X X X X CB2 X X X X X X X X X X X X X X X X X CB3 X X X X X X X X X X X X X X X CB4 X X X X X X X X X X CB5 X X X X X X X X X X CB6...

Page 610: ...is detected the DMCU causes an interrupt to the core by writing to the MCISR The memory location is overwritten by the DMCU with the error data but valid ECC making the contents of memory invalid For...

Page 611: ...gle bit error reporting is enabled Interrupt core for software scrubbing else uncorrectable if the read cycle is not part of a RMW cycle read Target Abort the Internal Bus read transaction else write...

Page 612: ...how the data flows through the ECC hardware for a read transaction Figure 94 DDR ECC Read Data Flow A8160 01 Main Memory MCU ECC Memory 64 bit Bus Address and Control Bus 8 bit Bus 64 bit Bus Error T...

Page 613: ...5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 S0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S3 1 1...

Page 614: ...e cycles with a multi bit error and ECC Error reporting is enabled the DMCU reports the interrupt in the MCISR and interrupts the core When the syndrome indicates a single bit error and single bit err...

Page 615: ...5678 9ABC DEF0H on AD 63 0 During the next NIBPTQ tenure this transaction is processes and the DDR SDRAM Control Block receives the data and must calculate the ECC code Using G Matrix in Figure 92 th...

Page 616: ...rior to writing the ECC to memory When the DMCU reads the address later the ECC mismatches and the error condition occurs see Section 7 5 ECC Interrupts Error Conditions on page 621 7 3 5 Memory Regio...

Page 617: ...remain powered with a battery backup and some agent must continue to refresh at the appropriate interval specified by the memory component datasheet This section defines a mechanism with which the 813...

Page 618: ...eset pin P_RST is asserted in order to float the output buffers In the specification Tfail is defined as the time when P_RST is asserted in response to the power rail going out of specification Tfail...

Page 619: ...completed on the memory bus 3 The CRU then asserts the internal bus reset to reinitialize all internal bus agents including the DMCU Note Internal bus reset is asserted in response to the assertion o...

Page 620: ...M preserves its memory image When power is restored the system asserts P_RST to the 81341 and 81342 While the 81341 and 81342 is reset CKE 1 0 is held low by memory controller After P_RST is deasserte...

Page 621: ...CU toggles one of the DMCISR bits from 0 to 1 an interrupt is generated to the core Table 371 shows how the DMCU responds to error conditions Note When ECC reporting is enabled with DECCR 1 or DECCR 0...

Page 622: ...G0 23 16 The DMCU loads DELOG0 7 0 with the syndrome that indicated the error The DMCU loads DELOG0 31 28 and DEAR0 31 2 with address where the error occurred In addition when an error occurs during a...

Page 623: ...ead cycle the DMCU signals a target abort to the agent The DMCU records the error type in DELOGx and the address in DEARx When DMCU detects a multi bit error during a write24 cycle and error reporting...

Page 624: ...MCU generates a single hardware interrupt DDR Memory Controller Unit Error Interrupt Pending to the Interrupt Controller Unit ICU for either a ECC error or a parity error ECC and parity error interrup...

Page 625: ...r SDUBR on page 633 Section 7 8 7 SDRAM Bank Size Register SBSR on page 635 Section 7 8 8 SDRAM 32 bit Region Size Register S32SR on page 637 Section 7 8 9 DDR ECC Control Register DECCR on page 638 S...

Page 626: ...ive Strength Manual Override Values Register DQPDSR on page 656 Section 7 8 28 MA Pad Drive Strength Manual Override Values Register MAPDSR on page 657 Section 7 8 29 MCLK Pad Drive Strength Manual Ov...

Page 627: ...t 25 drives Bank Address bit BA2 22 21 002 Reserved 20 07 00000H Address Bits MA 14 0 These fifteen bits are driven on the DDR SDRAM address bits MA 14 0 DDR SDRAM Mode Register and Extended Mode Regi...

Page 628: ...ration in MCLK periods Equation 19 RAS tRAS 1 where tRAS is from SPD 26 24 0002 RP Precharge Command Period in MCLK periods Equation 20 RP tRP 1 where tRP is from SPD 23 02 Reserved 22 20 0002 RCD Act...

Page 629: ...1 0 Applies to DDR2 SDRAM memory type only 00 Disabled 01 75 ohm 10 150 ohm 11 reserved 03 02 Reserved 02 02 DDR Type Only reflects DDR2 for 81341 and 81342 01 02 Data Bus Width Indicates the width o...

Page 630: ...peration 1 DQS Disabled for Singled ended operation 30 27 00002 RTCMD Read to Command non Read turnaround period in MCLK periods Equation 24 RTCMD tRTP X where tRTP is from SPD and X equals 2 for 400...

Page 631: ...CLK periods Equation 29 RC tRC 1 where tRC is from SPD 03 00 00002 WTRD Write to Read turnaround period in MCLK periods Equation 30 WTRD tCAS 1 BL 2 tWTR where BL 4 tCAS and tWTR are from SPD Table 37...

Page 632: ...ss the DDR SDRAM Warning The SDBR is internally used by the DDR MCU to create internal control signal After initializing the DDR MCU for normal operation wehen the user decides to reconfigure the DDR...

Page 633: ...ch address the DDR SDRAM Warning The SDUBR is internally used by the DDR MCU to create internal control signal After initializing the DDR MCU for normal operation when the user decides to reconfigure...

Page 634: ...shows the valid address range for the secondary memory window relative to the SDRAM space Note The Secondary SDRAM memory space must never be larger than the total SDRAM size defined by the SBSR or 2...

Page 635: ...rth and south internal buses before accessing the DDR MCU again to allow ample time for the new values to settle Table 380 SDRAM Bank Size Register SBSR Sheet 1 of 2 Bit Default Description 31 27 0000...

Page 636: ...y subsystem technology 002 512 Mbit 012 1 Gbit 102 2 Gbit 112 Reserved Table 380 SDRAM Bank Size Register SBSR Sheet 2 of 2 Bit Default Description PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 3...

Page 637: ...he DDR SDRAM Table 381 DDR SDRAM 32 bit Region Size Register S32SR Bit Default Description 31 30 002 Reserved 29 20 000H 32 bit Region Size indicates the size of the 32 bit region at the base of Bank0...

Page 638: ...abled 1 ECC Enabled 02 02 Single Bit Error Correction Enable Enables or disables the correction of a single bit error 0 Disable single bit error correction 1 Enable single bit error correction 01 02 M...

Page 639: ...le 383 DDR ECC Log Registers DELOG0 DELOG1 Sheet 1 of 2 Bit Default Description 31 28 0H Upper ECC Address The upper 4 bits of the 36 bit ECC Address is stored in this 4 bit field when an ECC error is...

Page 640: ...r 11 09 0002 Reserved 08 02 ECC Error Type Indicates the type of error that occurred at this address 0 Single Bit Error 1 Multi Bit Error 07 00 00H Syndrome Holds the syndrome value that indicated the...

Page 641: ...Address Registers DEAR0 DEAR1 Bit Default Description 31 02 0 Error Address For a 64 bit wide DDR Memory bus interface this field stores the lower 29 bits of the QWORD address in bits 31 03 that resu...

Page 642: ...pper Address Registers DECUAR0 DECUAR1 Table 385 DDR ECC Context Address Registers DECAR 0 DECAR 1 Bit Default Description 31 02 Reserved 30 05 0000000H ADMA Error Descriptor Address Bits 30 5 of this...

Page 643: ...nnel Number Stores the ADMA channel number when an ECC error occurs The DMA type is read from the DDR ECC Log Registers DELOG0 DELOG1 on page 639 01 00 002 Reserved PCI IOP Attributes Attributes 28 24...

Page 644: ...As 01102 Reserved 01112 Messaging Unit 10002 Reserved 10012 SMBus All other IDs are reserved Note This field is only valid when the Port ID in this register bits 19 16 indicates the north or the south...

Page 645: ...he address a 16 byte address in bits 31 04 that resulted in a parity error In 32 bit DDR memory mode this field stores the lower 29 bits of the address an 8 byte address in bits 31 03 that resulted in...

Page 646: ...Descriptor Address Bits 30 5 of this bit field stores the ADMA descriptor address 30 05 when a parity error occurs Note that ADMA descriptors are 32 byte aligned 30 05 ADMA Descriptor Address 30 05 04...

Page 647: ...r the same detected error logged in bit 08 Parity Error 0 08 02 Parity Error 0 Indicates the DMCU detected an Parity error and recorded the error in DPLOG 0 No error detected 1 Error detected and reco...

Page 648: ...H 1 transaction 2H 2 transactions 3H 3 transactions FH 15 transactions 0H 16 transactions Note The MU Port Transaction Count is always set to 1H 19 16 1H ADMA 2 Port Transaction Count Number of transa...

Page 649: ...tions 0H 16 transactions 03 00 0H North Internal Bus Transaction Count Number of transactions the north internal bus port can have processed in a single tenure of the DDR SDRAM 1H 1 transaction 2H 2 t...

Page 650: ...action When a north internal bus transaction port request is detected after the count has been exceeded by the current transaction the transaction is preempted at the next burst length boundary The cu...

Page 651: ...rved 12 00 000H Refresh Interval Programs number of clocks that trigger a request for a refresh cycle on DDR SDRAM interface When all zeroes refresh cycles are disabled See Section 7 3 1 5 Refresh Cou...

Page 652: ...ength 10 09 012 15 Ohm Adjust Control This field provides control to further adjust the value for all the 15 ohm drive strength selection made using RCOMP Pad Drive Strength Select RPDSR on page 654 0...

Page 653: ...opposed to the manually programming the values An external calibration resistor is referenced via the MCAL 1 0 pins to dynamically adjust the slew rate and drive strength in order to compensate for te...

Page 654: ...using DDR RCOMP Control Register DRCR on page 652 0002 50 ohm Drive strength 0012 35 ohm Drive strength 0102 25 ohm Drive strength 0112 17 9 ohm Drive strength 1002 15 ohm Drive strength All other va...

Page 655: ...er based on the loading of the DDR SDRAM Memory Subsystem Table 399 DQ Pad ODT Drive Strength Manual Override Values Register DQPODSR Bit Default Description 31 12 00000H Reserved 11 06 1000002 N ODT...

Page 656: ...le 400 DQ Pad Drive Strength Manual Override Values Register DQPDSR Bit Default Description 31 22 000H Reserved 21 15 10000002 N drive strength Manual override values for DQ 63 0 pad 14 08 10000002 P...

Page 657: ...e Values Register ADPDSR Bit Default Description 31 22 000H Reserved 21 15 10000002 N drive strength Manual override values for BA 2 0 MA 13 0 WE RAS CAS ODT 1 0 pad 14 08 10000002 P drive strength Ma...

Page 658: ...gth Manual Override Values Register MPDSR Bit Default Description 31 22 000H Reserved 21 15 10000002 N drive strength Manual override values for M_CK 2 0 and M_CK 2 0 pad 14 08 10000002 P drive streng...

Page 659: ...ve Strength Manual Override Values Register CKEPDSR Bit Default Description 31 22 000H Reserved 21 15 10000002 N drive strength Manual override values for CKE 1 0 and CS 1 0 pad 14 08 10000002 P drive...

Page 660: ...ay Register 0 DLLR0 Bit Default Description 31 29 0002 Reserved 28 24 011112 Data Strobe Slave Delay Selects the number of slave delay elements for DQS1 Recommended value is 011012 Note Slave determin...

Page 661: ...er 1 DLLR1 Bit Default Description 31 29 0002 Reserved 28 24 011112 Data Strobe Slave Delay Selects the number of slave delay elements for DQS3 Recommended value is 011012 Note Slave determines the nu...

Page 662: ...er 2 DLLR2 Bit Default Description 31 29 0002 Reserved 28 24 011112 Data Strobe Slave Delay Selects the number of slave delay elements for DQS5 Recommended value is 011012 Note Slave determines the nu...

Page 663: ...er 3 DLLR3 Bit Default Description 31 29 0002 Reserved 28 24 011112 Data Strobe Slave Delay Selects the number of slave delay elements for DQS7 Recommended value is 011012 Note Slave determines the nu...

Page 664: ...ol Register 0 SDCR0 on page 628 Table 408 DLL Delay Register 4 DLLR4 Bit Default Description 31 29 0002 Reserved 28 24 011112 Receive Enable Master Delay Selects the number of master delay elements fo...

Page 665: ...rmine the optimum receive enable pulse width location The Receive Enable Result bit is cleared by setting the Receive Enable Reset Bit The Receive Enable Result bit must be reset through each iteratio...

Page 666: ...Inches Receive Enable Slave Delay 2 0012 4 0012 6 0012 8 0012 For DDR2 533MHz 50 Ohms Trace Length Inches Receive Enable Slave Delay 2 0012 4 0012 6 0012 8 0102 For DDR2 533MHz 60 Ohms Trace Length I...

Page 667: ...gth Inches Receive Enable Slave Delay 2 001012 4 011012 6 101012 8 111102 For DDR2 533MHz 50 Ohms Trace Length Inches Receive Enable Slave Delay 2 000112 4 011012 6 110012 8 001002 For DDR2 533MHz 60...

Page 668: ...gure 99 Using the initial DQS value the algorithm proceeds to find the rising edge of DQS The DQS signal rising edge is searched by shifting the DLLRCVEREN pulse either left or right depending on the...

Page 669: ...0x50 Set Initial Value of DLLRCVER Delay using a recommended initial value dqs_value sample_dqs dllrcver_value Take first sample of DQS with current DLLRCVER Delay Set direction and compare value to...

Page 670: ...f dllrcver_value 0 dllrcver_value 0 Write new DLLRCVER value treg MCU_DLLRCVER 1 16 fine dllrcver_value 0x1f coarse dllrcver_value 5 0x7 MCU_DLLRCVER treg coarse 8 fine Reset the MCU FIFOs sdcr0_val M...

Page 671: ...o guarantee previous write operation MCU_DLLRCVER Read a DDR SDRAM Memory Location this memory read causes the auto calibration circuit to sample the DQS signal val ddr_mem_addr If not defined as a st...

Page 672: ...v na rv na rv na rv na rv na rv na rv na rv na rv na rv na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na rv na rv na rv na rv na rv na rv na rv na rv na Attribute...

Page 673: ...4 0 31 rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na rv na rv na rv na rv na rv na rv na rv na rv na A...

Page 674: ...n 31 22 000H Reserved 21 15 xH N drive strength Drive Strength computed by RCOMP for 50 Ohm RCOMP 14 08 xH P drive strength Drive Strength computed by RCOMP for 50 Ohm RCOMP 07 04 0H Reserved 03 00 0H...

Page 675: ...e 128 bit wide port with data parity protection ECC supported on 32 bit data width The SRAM interface provides a direct connection to a high bandwidth and reliable memory subsystem An 7 bit Error Corr...

Page 676: ...hin the memory array the SMCU must correct the error if possible while delivering the data to the initiator Correcting the memory location is referred to as scrubbing the array The SMCU relies on soft...

Page 677: ...ess Each device connects to the SMCU using a separate read port and write port Each port provides a 128 bit data path The ports are described in the next sub sections 8 3 1 1 1 North Internal Bus Port...

Page 678: ...3 1 3 Memory Transaction Queues There are one set of transaction queues for transactions which address the SRAM Memory Space from the north internal bus The transaction queues are located in each res...

Page 679: ...and writes For reads this logic compares the ECC codes read with the locally generated ECC code If the codes mismatch then the Error Correction Logic determines the error type For a single bit error...

Page 680: ...rency With the queueing of SRAM transactions in multiple ports coherency of memory must be maintained The SMARB maintains memory coherency by ensuring that all writes to a given memory address are com...

Page 681: ...required Refer to Section 427 SRAM Parity Control and Status Register SPARCSR on page 706 8 3 2 2 SRAM Read Sequence Read transactions require ECC codes to be calculated and compared with the ECC retu...

Page 682: ...the transaction should be claimed If the address falls in the SRAM address range indicated by the SRAMBAR and SRAMUBAR the SMCU claims the transaction 2 Once the SMARB selects the highest priority por...

Page 683: ...ents a 256 bit data path to the SRAM array but a 7 bit error correction code per every 32 bit datum For example SCB0 6 0 for DQ 31 0 SCB1 6 0 for DQ 63 32 SCB2 6 0 for DQ 95 64 and so on resulting in...

Page 684: ...a and ECC else Partial Write Read entire 32 bit data word from memory Merge the new data portion with the data from memory Generate the new ECC with the G matrix Write new data and ECC Figure 101 show...

Page 685: ...ata is written back to the array If a multi bit error is detected the SMCU causes an interrupt to the core by writing to the MCISR The memory location is overwritten by the SMCU with the error data bu...

Page 686: ...enabled Interrupt core for software scrubbing else uncorrectable if the read cycle is not part of a RMW cycle read Target Abort the Internal Bus read transaction else write requiring RMW Merge the ne...

Page 687: ...ECC hardware for a read transaction Figure 103 ECC Read Data Flow ECC 256 bit Data Path SMCU SRAM Memory Array ECC Memory D 31 0 H Matrix Look Up Table Caculate ECC G Matrix Caculate Syndrome Data Cor...

Page 688: ...t Syndrome ECC Check Bits E 6 0 E 6 E 5 E 4 E 3 E 2 E 1 E 0 E 6 E 5 E 4 E 3 E 2 E 1 E 0 E6 40H X D15 45H X X X E5 20H X D14 51H X X X E4 10H X D13 43H X X X E3 08H X D12 61H X X X E2 04H X D11 25H X X...

Page 689: ...he core Write cycles are posted to the memory transaction queues and already completed to the initiating master For write cycles with a multi bit error and ECC Error reporting is enabled the SMCU repo...

Page 690: ...G Matrix in Figure 102 the SRAM Control Block creates each check bit by XORing the appropriate bits in the row Using 9ABC DEF0H the ECC code generated is 11H This code is written with the data to the...

Page 691: ...xplains how software is responsible for correcting an error in the memory array once it has been detected by the ECC logic The SMCU implements the SECTST register providing the programmer the ability...

Page 692: ...e port and before it is written to the data queue For read requests made to an SMCU port the direct memory port interface performs the following tasks before delivering data checks for ECC on the data...

Page 693: ...bit XORing the data bits as shown in Table 417 As an example the parity calculation for the lowest order byte of the data bus D 7 0 is calculated as follows Note The direct memory port does not suppor...

Page 694: ...direct memory port does not support address parity Equation 33 DATA_PARITY_RESULT D_PARITY0 XOR D 0 XOR D 1 XOR D 2 XOR D 3 XOR D 4 XOR D 5 XOR D 6 XOR D 7 XOR BE 0 A non zero result from the above o...

Page 695: ...n the error in SELOG 23 16 and interrupts the core If the SMCU detects an ECC error during a read or write cycle SMCISR 0 is set to 1 Whenever the SMCU toggles the SMCISR 0 bit from 0 to 1 an interrup...

Page 696: ...r SMCU records requester of transaction that resulted in an error in SELOG 23 16 The SMCU loads SELOG 7 0 with the syndrome that indicated the error The SMCU loads SECAR 31 2 and SECUAR with address w...

Page 697: ...rnal bus initiator of a multi bit error by returning a target abort The SMCU records the error type in SELOG and the address in SECAR and SECUAR When SMCU detects a multi bit error during a write25 cy...

Page 698: ...detected on any of the SMCU ports and parity is enabled the SMCU records the requesting port that detected the parity error in the SPCSR 19 16 and interrupts the core Refer to the Section 8 6 8 SRAM...

Page 699: ...r Register Section Register Name Acronym Page Section 8 6 1 SRAM Base Address Register SRAMBAR on page 700 Section 8 6 2 SRAM Upper Base Address Register SRAMUBAR on page 700 Section 8 6 3 SRAM ECC Co...

Page 700: ...MBAR Bit Default Description 31 20 1111 1111 11102 SRAM Base Address Provide lower twelve bits of SRAM base address Default SRAM base address is 0 FFE0 0000H 19 00 0 0000H Reserved PCI IOP Attributes...

Page 701: ...nable Enables or disables the correction of a single bit error 0 Disable single bit error correction 1 Enable single bit error correction 01 02 Multi Bit Error Reporting Enable Enables or disables the...

Page 702: ...2 Bit Default Description 31 28 0H Upper ECC Address The upper 4 bits of the 36 bit ECC Address is stored in this 4 bit field when an ECC error is logged For example the lower 32 bits are logged in t...

Page 703: ...ng a read or write transaction 0 Read error 1 Write Error 11 09 0002 Reserved 08 02 ECC Error Type Indicates the type of error that occurred at this address 0 Single Bit Error 1 Multi Bit Error 07 00...

Page 704: ...4 SRAM ECC Address Register SEAR Bit Default Description 31 02 0 Error Address Stores the lower 30 bits of the address that resulted in a single bit or multi bit error 01 00 002 Reserved PCI IOP Attri...

Page 705: ...ons result in an ECC error Table 426 SRAM ECC Test Register SECTST Bit Default Description 31 07 00 0000H Reserved 06 00 00H ECC Mask 7 bit ECC mask Each bit of the generated ECC is XORed with the app...

Page 706: ...012 Application DMAs 01102 Reserved 01112 Messaging Unit 10002 Reserved 10012 SMBus All other IDs are reserved Note This field is only valid when the Port ID in this register bits 19 16 indicates the...

Page 707: ...of associated log register For error details see Section 8 3 4 Byte Parity Checking and Generation on page 692 Table 428 SRAM Parity Address Registers SPAR Bit Default Description 31 02 0000 0000H Err...

Page 708: ...atus Register SMCISR Bit Default Description 31 05 0000 000H Reserved 09 02 Parity N Indicates that the SMCU detected a Parity error while SMCISR 8 was set 0 No error detected 1 Error detected 08 02 P...

Page 709: ...Peripheral Bus signals which consist of address data control status Peripheral Bus Read and write transactions Peripheral Bus configuration and Flash Memory Support Registers This chapter also serves...

Page 710: ...ipheral Bus Multi byte read requests and multi byte write requests are supported differently by the PBI Write requests are limited to a maximum of 4 bytes only and must not span a DWORD boundary The P...

Page 711: ...ables and direction All output control status signals are three state A peripheral read may be either non burst or burst A non burst read ends after one data transfer to a single location When the dat...

Page 712: ...s in a manner consistent with the programmed bus width 8 bit region A 1 0 provide the demultiplexed byte address for a read burst 16 bit region A 2 1 provide the demultiplexed short word address for a...

Page 713: ...e bursted transaction Address bits A 24 3 provide the upper address of the current access and is a constant during the address Ta wait state Tw and data cycles Td cycles A 2 1 are used for an 16 bit w...

Page 714: ...ndow must always represent a single flash bus data cycle strb strh The peripheral chip enables PCE 1 0 activate the appropriate Peripheral window when the address falls within one of the Peripheral ad...

Page 715: ...he definition of recovery wait states are the number of cycles between the data arrival on D 7 0 and the address for the next Peripheral transaction Address to data and recovery wait states are progra...

Page 716: ...ively Refer to Table 432 for the programmable address to data data to data and recovery wait states These numbers are based on a 66 MHz internal clock for the PBI interface Figure 110 120 ns Flash Bur...

Page 717: ...uests the PBI supports multi byte write requests by breaking the writes on the PBI bus into multiple single data write transactions The number of single data write transactions initiated on the PBI bu...

Page 718: ...Name Acronym Page Section 9 3 1 PBI Control Register PBCR on page 719 Section 9 3 2 PBI Status Register PBISR on page 719 Section 9 3 4 PBI Base Address Register 0 PBBAR0 on page 721 Section 9 3 5 PB...

Page 719: ...rw na rw na rv na rv na rv na rv na rw na rw na rw na rw na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rw na Attribute Legend RV Reserved PR Preserved RS...

Page 720: ...ize of the memory window set in a limit register For a 1 Mbyte memory window only bit 20 through bit 31 of the base address from the PBI Base Address Register 0 PBBAR0 are relevant to the PBI when dec...

Page 721: ...ta to Data wait states Others 20 Data to Data wait states Note By default the data to data wait states are 20 since it is the same as the address to data wait states 08 06 1112 Recovery Cycle Wait Sta...

Page 722: ...BI Limit Register 0 PBLR0 Bit Default Description 31 12 FE000H Memory Window 0 Limit This value determines the memory block size required for the Memory Window 0 Defaults to an 32MB Peripheral Window...

Page 723: ...Data to Data wait states 011 8 Data to Data wait states 100 12 Data to Data wait states 101 16 Data to Data wait states Others 20 Data to Data wait states Note By default data to data wait states are...

Page 724: ...Table 440 PBI Limit Register 1 PBLR1 Bit Default Description 31 12 00000H Memory Window 1 Limit Determines the memory block size required for the Memory Window 1 11 00 000H Reserved PCI IOP Attribute...

Page 725: ...SDRAM interface and the PCI X interface 15 12 00112 Pull Up Slew Rate Control PSLW 3 0 Tunes the slew rate of the p drivers of all the pins with the exception of the high speed serial interfaces the S...

Page 726: ...vided by 2 012 3 1 Indicates that the Internal bus is running at the Core Frequency divided by 3 102 4 1 Indicates that the Internal bus is running at the Core Frequency divided by 4 112 Reserved 18 1...

Page 727: ...erved 16 x2 CLK_SRC_PCIE 15 x2 INTERFACE_SEL_PCIX 14 x2 Reserved 13 x2 LK_DN_RST_BYPASS 12 x2 PCIX_PULLUP 11 10 xx2 Reserved 09 07 xxx2 Reserved 06 x2 BOOT_WIDTH_8 Note This bit reflects the inverted...

Page 728: ...ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na Attribute Legend RV Reserved PR Preserved RS Read Set RW Read Write RC Read Clear RO Read Only NA...

Page 729: ...41 and 81342 supports two Intel XScale processors and provides the following features to facilitate the co existence of two cores Core ID Inter Processor Reset Inter Processor Interrupt Each Intel XSc...

Page 730: ...reset The cores can initiate and event to another core by writing its co processor registers The IPC monitors issued events from all cores and then routes the interrupt or reset to the appropriate co...

Page 731: ...r Reset Cause Status Register RCSR Refer to Section 448 Reset Cause Status Register RCSR on page 736 This register provides a mechanism for software to identify the cause of the a reset for example a...

Page 732: ...in strap that can be used control whether coreID1 stays in reset after the system reset is de asserted When the strap is pulled low coreID1 stays in reset after the main system reset is de asserted Th...

Page 733: ...ld also run but eventually wait in a software loop waiting for the software interrupt pending register to be written by the master core 3 After the master core coreID0 has completed enough initializat...

Page 734: ...eID0 will setup the SRAM Base Address Registers to 0 0000 0000H This would allow the core access to be claimed by the SRAM MCU during boot 5 coreID0 would then clear the HOLD_X1_IN_RST bit to release...

Page 735: ...ld Coprocessor Register CRn Field CIDR Core Identification Register CIDR 0 Register 0 RCSR Reset Cause Status Register RCSR 1 Register 0 SINTGENR Software Interrupt Generation Register SINTGENR Regist...

Page 736: ...at this core was reset by the Initiate Core Processor Reset bit located in the ATU X PCSR Register 05 02 Watchdog Timer Internal Bus Reset When set this bit indicates that the internal bus was reset d...

Page 737: ...4 Core Dependent coreID This 4 bit field provides the core identification number of the core to which the interrupt is to be targeted 23 08 0000H Reserved 07 05 0002 Preserved 04 00 000002 Interrupt S...

Page 738: ...450 Targeted Reset Register TARRSTR Bit Default Description 31 01 0000 0000H Reserved 03 00 00002 Targeted Core Identification coreID This field identifies the coreID of the core that will be the tar...

Page 739: ...pt service come from many sources and are prioritized such that instruction execution is redirected only when an exception interrupt request is of higher priority than that of the executing task On th...

Page 740: ...ssociated interrupts are fully demultiplexed into the ICU however In order to provide the executing software with the knowledge of interrupt source coprocessor mapped status registers describe the sou...

Page 741: ...to address the instruction that caused the exception R13 is banked across exception modes to provide each exception handler with a private stack pointer SP The fast interrupt mode also banks R8 to R12...

Page 742: ...al interrupt IRQ In addition while an FIQ exception is executing the IRQ exception is masked out When an exception is taken by the processor the Program Counter PC is loaded with the vector associated...

Page 743: ...ption Handler Routines Software handler to nest certain exceptions i e FIQ and IRQ These items are established in memory as part of the initialization procedure 11 3 4 1 Nesting FIQ and IRQ Exceptions...

Page 744: ...is a level detect input only These pins are internally synchronized These pins only act as interrupt inputs when they are unmasked in the INTCTL 3 0 registers These pins can also function as general...

Page 745: ...used as an interrupt pin XINT4 GPIO 12 This is a bi directional pin This pin can act as an input XINT4 and drive the XINT4 input of the Interrupt Controller The Interrupt Controller Unit input XINT4 c...

Page 746: ...ects of mailbox registers and doorbell registers Writes to the message registers may optionally cause interrupts Doorbell Registers allow the 81341 and 81342 to assert the PCI interrupt signals and al...

Page 747: ...0 Note that when the 81341 and 81342 acts as an endpoint with the PCI X interface only twelve interrupt inputs XINT 15 4 are available instead of sixteen as the remaining four become outputs P_INT D...

Page 748: ...terrupt vector generation is enabled and there are multiple requests pending either in the FINTSRC 3 0 or the IINTSRC 3 0 registers the prioritization selects a highest priority active source for each...

Page 749: ...81341 and 81342 does not use all 128 possible sources ICU registers reside in Coprocessor 6 CP6 They may be accessed manipulated with the MCR MRC STC and LDC instructions The instruction CRn field den...

Page 750: ...g Intel Xscale Processor PMU Interrupt Pending Messaging Unit Interrupt Pending MU Inbound Post Queue Interrupt Pending Peripheral Bus Interface Error SRAM MCU Error ATUX Error ATUE Error Internal Bus...

Page 751: ...sters depending on the value in INTSTR 3 0 To provide the best latency for high performance event driven activities the Application DMAs interrupts are fully demultiplexed into the interrupt source re...

Page 752: ...ble 454 Note The UART and I2C Bus Interface Unit interrupt sources are combined as a single interrupt and include both normal and error conditions within the respective units Table 454 Normal Interrup...

Page 753: ...Intel XScale processor L2 Cache BIU Error Logging Register ERRLOG L2 cache single bit ECC error ADMA Channel 2 0 Channel Status Register 2 0 IB Master Abort PCI Master Abort PCI Target Abort master Un...

Page 754: ...upt the co processor register has to be written again By writing the co processor register the ISN is transferred to the targeted core interrupt controller The receiving core s interrupt controller de...

Page 755: ...ered to IRQ IINTSRC0 0000 0000H All IRQ interrupts 31 0 inactive IINTSRC1 0000 0000H All IRQ interrupts 63 32 inactive IINTSRC2 0000 0000H All IRQ interrupts 95 64 inactive IINTSRC3 0000 0000H All IRQ...

Page 756: ...rrupt Base Register 2 Register 0 Reserved Register 1 INTSIZE Interrupt Size Register Register 2 IINTVEC IRQ Interrupt Vector Register Register 3 FINTVEC FIQ Interrupt Vector Register Register 4 IPIPND...

Page 757: ...Register 2 Register 2 IPR3 Interrupt Priority Register 3 Register 3 IPR4 Interrupt Priority Register 4 Register 4 IPR5 Interrupt Priority Register 5 Register 5 IPR6 Interrupt Priority Register 6 Regis...

Page 758: ...ed for a 512 Byte ISR memory range and the upper 16 bits for a 64 KByte ISR memory range etc Table 458 Interrupt Base Register INTBASE Bit Default Description 31 09 0000 00H Interrupt Base These bits...

Page 759: ...ZE Bit Default Description 31 04 0000000H Reserved 03 00 0H ISR Memory Range Size These bits define the size of the ISR memory range INTSIZE ISR Range Size ISR Size per Source 0 Disabled 1 512 bytes 4...

Page 760: ...Before returning to User Mode from Interrupt Mode the software reads the IINTVEC register and process any lower priority IRQ sources that are active When there are no longer any active IRQ sources a r...

Page 761: ...Before returning to User Mode from Interrupt Mode the software reads the FINTVEC register and process any lower priority FIQ sources that are active When there are no longer any active FIQ sources a r...

Page 762: ...cessor Interrupt Pending Register IPIPNDR Bit Default Description 31 00 0000 0000H Inter Processor Interrupt Pending All the bits in this register have the same behavior Each bit in this register is i...

Page 763: ...TU X Start BIST Interrupt Pending 14 02 ATU E Inbound Message Interrupt 13 02 Messaging Unit Inbound Post Queue Interrupt Pending 12 02 Messaging Unit Interrupt Pending 11 02 I2C Bus Interface 1 Inter...

Page 764: ...Pending 20 02 UART 1 Interrupt Pending 19 02 UART 0 Interrupt Pending 18 08 0000H Reserved 07 02 XINT15 Interrupt Pending Source of this interrupt is the GPIO 7 pin 06 02 XINT14 Interrupt Pending Sour...

Page 765: ...ved 24 02 Reserved 23 02 Reserved 22 02 Reserved 21 02 Reserved 20 02 Reserved 19 02 Reserved 18 02 Reserved 17 02 Reserved 16 02 Reserved 15 02 Reserved 14 02 Reserved 13 02 Reserved 12 02 Reserved 1...

Page 766: ...rupt Pending 14 02 ATUE Interrupt Message D Pending 13 02 ATUE Interrupt Message C Pending 12 02 ATUE Interrupt Message B Pending 11 02 ATUE Interrupt Message A Pending 10 05 02 Reserved 04 02 IMU Int...

Page 767: ...nterrupt Mask 0 Masked 1 Not Masked 25 02 XINT1 Interrupt Mask 0 Masked 1 Not Masked 24 02 XINT0 Interrupt Mask 0 Masked 1 Not Masked 23 19 02 Reserved 18 02 Intel XScale Processor Cache Interrupt Mas...

Page 768: ...Masked 8 02 Timer 0 Interrupt Mask 0 Masked 1 Not Masked 7 02 Reserved 6 02 Watch Dog Timer Interrupt Mask 0 Masked 1 Not Masked 5 02 ADMA Channel 2 End Of Chain Interrupt Mask 0 Masked 1 Not Masked...

Page 769: ...Masked 1 Not Masked 0 02 ADMA Channel 0 End Of Transfer Interrupt Mask 0 Masked 1 Not Masked Table 467 Interrupt Control Register 0 INTCTL0 Sheet 3 of 3 Bit Default Description Memory Coprocessor Att...

Page 770: ...errupt Mask 0 Masked 1 Not Masked 24 02 Memory Controller Unit Error Interrupt Mask 0 Masked 1 Not Masked 23 02 ATU Error Interrupt Mask 0 Masked 1 Not Masked 22 02 ATU Configuration Register Write In...

Page 771: ...t Masked 02 02 XINT10 Interrupt Mask Source of this interrupt is the GPIO 2 pin 0 Masked 1 Not Masked 01 02 XINT9 Interrupt Mask Source of this interrupt is the GPIO 1 pin 0 Masked 1 Not Masked 00 02...

Page 772: ...Reserved 30 02 South Internal Bus Bridge Error Interrupt Mask 0 Masked 1 Not Masked 29 01 02 Reserved 0 02 Inter Processor Interrupt Mask 0 Masked 1 Not Masked Memory Coprocessor Attributes Attribute...

Page 773: ...MSI X Table Write Interrupt Pending 0 Masked 1 Not Masked 14 02 ATUE Interrupt Message D Pending 0 Masked 1 Not Masked 13 02 ATUE Interrupt Message C Pending 0 Masked 1 Not Masked 12 02 ATUE Interrup...

Page 774: ...Masked 00 02 I2C Bus Interface 2 Interrupt Pending 0 Masked 1 Not Masked Table 470 Interrupt Control Register 3 INTCTL3 Sheet 2 of 2 Bit Default Description Memory Coprocessor Attributes Attributes 2...

Page 775: ...eering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 26 02 XINT2 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 25 02 XINT1 In...

Page 776: ...IRQ 1 Interrupt Directed to Internal FIQ 9 02 Timer 1 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 8 02 Timer 0 Interrupt Steering 0 Interrupt Directed...

Page 777: ...nd Of Chain Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 0 02 ADMA Channel 0 End Of Transfer Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 I...

Page 778: ...errupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 24 02 Memory Controller Unit Error Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 23...

Page 779: ...cted to Internal FIQ 02 02 XINT10 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 01 02 XINT9 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Int...

Page 780: ...NTSTR2 Bit Default Description 31 02 Reserved 30 02 South Internal Bus Bridge Error Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 29 01 02 Reserved 00 02...

Page 781: ...ed 15 02 MU MSI X Table Write Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 14 02 ATUE Interrupt Message D Steering 0 Interrupt Directed to Internal IRQ...

Page 782: ...upt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Internal FIQ 00 02 I2C Bus Interface 2 Interrupt Steering 0 Interrupt Directed to Internal IRQ 1 Interrupt Directed to Interna...

Page 783: ...and unmasked by INTCTL0 27 02 XINT3 Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0 1 Interrupting and steered to internal IRQ exception and unmasked by INT...

Page 784: ...ception and unmasked by INTCTL0 11 02 I2C Bus Interface 1 Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0 1 Interrupting and steered to internal IRQ exceptio...

Page 785: ...ked by INTCTL0 1 02 ADMA Channel 0 End Of Chain Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0 1 Interrupting and steered to internal IRQ exception and unma...

Page 786: ...o internal IRQ exception and unmasked by INTCTL1 24 02 Memory Controller Unit Error Interrupt when set an error condition exists within the MCU The bit indicates one of the following conditions A sing...

Page 787: ...ked by INTCTL1 3 02 XINT11 Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL1 1 Interrupting and steered to internal IRQ exception and unmasked by INTCTL1 2 02...

Page 788: ...lt Description 31 02 Reserved 30 02 South Internal Bus Bridge Error Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL2 1 Interrupting and steered to internal IR...

Page 789: ...rrupting or Not steered to internal IRQ exception or masked by INTCTL3 1 Interrupting and steered to internal IRQ exception and unmasked by INTCTL3 14 02 ATUE Interrupt Message D 0 Not Interrupting or...

Page 790: ...NTCTL3 01 02 ATU E Start BIST Interrupt 0 Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL3 1 Interrupting and steered to internal IRQ exception and unmasked by INTCTL3 00...

Page 791: ...nd unmasked by INTCTL0 27 02 XINT3 Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0 1 Interrupting and steered to internal FIQ exception and unmasked by INTCT...

Page 792: ...ception and unmasked by INTCTL0 11 02 I2C Bus Interface 1 Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0 1 Interrupting and steered to internal FIQ exceptio...

Page 793: ...ked by INTCTL0 1 02 ADMA Channel 0 End Of Chain Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL0 1 Interrupting and steered to internal FIQ exception and unma...

Page 794: ...internal FIQ exception and unmasked by INTCTL1 24 02 Memory Controller Unit Error Interrupt when set an error condition exists within the MCU The bit indicates one of the following conditions A single...

Page 795: ...ked by INTCTL1 3 02 XINT11 Interrupt Mask 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL1...

Page 796: ...Description 31 02 Reserved 30 02 South Internal Bus Bridge Error Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL2 1 Interrupting and steered to internal FIQ...

Page 797: ...ing or Not steered to internal FIQ exception or masked by INTCTL3 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL3 14 02 ATUE Interrupt Message D 0 Not Interrupting or Not...

Page 798: ...NTCTL3 01 02 ATU E Start BIST Interrupt 0 Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3 1 Interrupting and steered to internal FIQ exception and unmasked by INTCTL3 00...

Page 799: ...Default Description 31 30 002 ATU Start BIST Interrupt Priority 29 28 002 ATU E Inbound Message Interrupt Priority 27 26 002 Messaging Unit Inbound Post Queue Interrupt Priority 25 24 002 Messaging U...

Page 800: ...ghest order bit is first 002 High Priority 012 Medium High Priority 102 Medium Low Priority 112 Low Priority Table 484 Interrupt Priority Register 1 IPR1 Bit Default Description 31 30 002 XINT7 Interr...

Page 801: ...or IRQ the vector is selected according to a fixed priority based on bit location Highest order bit is first 002 High Priority 012 Medium High Priority 102 Medium Low Priority 112 Low Priority Table...

Page 802: ...rity 012 Medium High Priority 102 Medium Low Priority 112 Low Priority Table 486 Interrupt Priority Register 3 IPR3 Bit Default Description 31 30 002 Reserved 29 28 002 Messaging Unit Error Interrupt...

Page 803: ...n the FINTVEC or IINTVEC respectively Note When multiple interrupts at the same priority level are pending for either FIQ or IRQ the vector is selected according to a fixed priority based on bit locat...

Page 804: ...INTVEC respectively Note When multiple interrupts at the same priority level are pending for either FIQ or IRQ the vector is selected according to a fixed priority based on bit location Highest order...

Page 805: ...ity 29 28 002 ATUE Interrupt Message D Priority 27 26 002 ATUE Interrupt Message C Priority 25 24 002 ATUE Interrupt Message B Priority 23 22 002 ATUE Interrupt Message A Priority 21 10 002 Reserved 0...

Page 806: ...spectively Note When multiple interrupts at the same priority level are pending for either FIQ or IRQ the vector is selected according to a fixed priority based on bit location Highest order bit is fi...

Page 807: ...CP6 use the Coprocessor Access Register Figure 116 shows a diagram of the timer functions See also Figure 117 for the Programmable Timer state diagram When enabled a timer decrements the user defined...

Page 808: ...with the same 32 bit TCRx value Software can read or write the TCRx value whether the timer is running or stopped This lets the user monitor the count without using hardware interrupts When the TCRx v...

Page 809: ...value E1E1 E1E1H to the WDT Control register When enabled the WDT is initialized with FFFF FFFFH and begin to decrement towards 0000 0000H The software is required periodically to write the WDT initi...

Page 810: ...alue specified for TMRx tc in a write request TMRx enable Timer Enable Bit 1 READ Bit is available 1 internal bus clock after executing a read instruction from TMRx WRITE Writing a 1 enables the inter...

Page 811: ...interrupt can be selectively masked in the Interrupt Control INTCTL 1 0 registers Refer to the Interrupt Controller Unit Chapter for a description of interrupt controller operation After servicing the...

Page 812: ...0 TMRx csel1 0 0 IPND tip 0 TMRx enable 1 TMRx reload user value TMRx pri user value TMRx csel1 0 user value TMRx reload user value TMRx pri user value TMRx csel1 0 user value TC 1 IPND tip 1 TMRx en...

Page 813: ...ction 12 4 4 Timer Reload Register TRR0 1 on page 817 12 4 1 Power Up Reset Initialization Upon assertion of P_RST the timer registers are initialized to the values shown in Table 495 Table 494 Timer...

Page 814: ...11 16 1 Timer Clock internal bus clock 16 03 02 Timer Register Privileged Write Control TMRx pri 0 Privileged and User Mode Write Enabled 1 Privileged Mode Only Write Enabled 02 02 Timer Auto Reload E...

Page 815: ...er Auto Reload Enable TMRx reload bit 0 Hardware or software reset Refer to Section 19 2 Reset Overview on page 993 12 4 2 3 Bit 2 Timer Auto Reload Enable TMRx reload The TMRx reload bit determines w...

Page 816: ...Select TMRx csel1 0 User software programs the TMRx csel bits to select the Timer Clock TCLOCK frequency See Table 497 As shown in Figure 116 the internal bus clock is an input to the timer clock uni...

Page 817: ...is from 1H to FFFF FFFFH Avoid programming a value of 0 as it may prevent TINTx from asserting continuously See Section 12 5 Uncommon TCRX and TRRX Conditions on page 820 for more information User so...

Page 818: ...detects a zero count in WDT After servicing the interrupt SW needs to write a 1 to this bit to clear the pending request Note that the Watchdog timer must be setup to generate an interrupt Refer to S...

Page 819: ...riting 1E1E 1E1EH followed by E1E1 E1E1H to this register software can enable the WDT and reset the count value to FFFF FFFFH When read this register returns the current value contained in the WDT Onc...

Page 820: ...er Reload Register to zero before enabling the timer Table 503 details the conditions and results when these conditions are set Table 503 Uncommon TMRx Control Bit Settings TRRx TCRx Bit 2 TMRx reloa...

Page 821: ...ters Circular Queues The IMUs Circular Queue mechanism consists of eight queues Four of the queues are for queueing messages from Processor 0 to Processor 1 while the other four are for queueing messa...

Page 822: ...n enabled is signaled to that Intel XScale processor The IMU provides individual interrupt enables for each Door Bell bit see Section 13 6 2 Door Bell Enable Register DBER on page 834 and the ability...

Page 823: ...er processor by writing to the DBAR register The DBAR bits may only be cleared by the other processor Figure 118 Door Bell Registers as Viewed by Processor 0 and Processor 1 Door Status Field of DBCR...

Page 824: ...four Receive Queues as detailed in Table 504 Note that in Table 504 for a given processor s Send Queue there is a corresponding Receive Queue in the other processor and visa versa The benefit of this...

Page 825: ...lue of the Size field The Send Queue Reset Request field is a request from the other processor to reinitialize the Put Get Pointers for the Send Queue Setting the Send Queue Reset field will reinitial...

Page 826: ...ead Only Get Pointer Read Write Send Queue Put Get Pointer X Receive Queue Put Get Pointer Register X Send Queue Control Register X S Q R R S Q R Queue Size Read Write Queue Size Read Only Receive Que...

Page 827: ...ueue Management Following a initialization the Receive Queue registers are set to their default value The Receive Queue will be configured and managed using the following steps 1 Read the 36 bit local...

Page 828: ...R e c e iv e Q u e u e 3 N o t E m p t y S e n d Q u e u e 3 N o t F u ll R e c e iv e Q u e u e 2 N o t E m p t y S e n d Q u e u e 2 N o t F u ll R e c e iv e Q u e u e 1 N o t E m p t y S e n d Q u...

Page 829: ...of the DBCR 14 0 the 4 bit Highest Priority Door Bell field DBCR 31 28 represents the lowest order bit set The two fixed priority schemes are detailed in Table 506 Table 506 Fixed Priority Scheme for...

Page 830: ...n page 837 Section 13 6 7 Send Queue Lower Base Address Register 0 SQLBAR0 on page 838 Section 13 6 8 Send Queue Upper Base Address Register 0 SQUBAR0 on page 838 Section 13 6 9 Receive Queue Put Get...

Page 831: ...Lower Base Address Register 3 SQLBAR3 on page 854 Section 13 6 32 Send Queue Upper Base Address Register 3 SQUBAR3 on page 855 Section 13 6 33 Receive Queue Put Get Pointer Register 3 RQPG3 on page 85...

Page 832: ...R0NE 9 Reserved 2 S1NF 10 Reserved 3 R1NE 11 Reserved 4 S2NF 12 Reserved 5 R2NE 13 Reserved 6 S3NF 14 Reserved 7 R3NE 15 None Default Value 23 02 Receive Queue 3 Not Empty R3NE When set Receive Queue...

Page 833: ...d Queue 0 Put Pointer minus Send Queue 0 Get Pointer does not equal Send Queue 0 Size 15 02 Reserved 14 00 0000H Door Bell Status DBSTAT These bits show the Door Bell Status set by the other processor...

Page 834: ...rted to the Intel XScale processor when Send Queue 2 is not Full 19 02 Enable Receive Queue 1 Not Empty Interrupt ER1NE When set an interrupt request is asserted to the Intel XScale processor when the...

Page 835: ...20 16 12 8 4 0 31 rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rs na rs na rs na rs na rs na rs na rs na rs na rs na rs na rs na rs na rs na rs...

Page 836: ...r adding new messages Table 512 Send Queue Put Get Pointer Register 0 SQPG0 Bit Default Description 31 16 0000H Send Queue 0 Get Pointer Index of the next queue entry for the other processor to read i...

Page 837: ...0R and SQ0RR bits in the SQCR0 will be reinitialized along with the Put Get Pointers 30 02 Send Queue 0 Reset Request SQ0RR The other processor is requesting that Send Queue 0 be reinitialized by retu...

Page 838: ...a rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na Attribute Le...

Page 839: ...sages have been added to Receive Queue 0 Table 516 Receive Queue Put Get Pointer Register 0 RQPG0 Bit Default Description 31 16 0000H Receive Queue 0 Get Pointer Index of the next queue entry to read...

Page 840: ...turning the Put Get pointers to their default values Note The reinitialization of Receive Queue 0 will not take effect until the Receive Queue 0 Reset bit RQ0R in the RQCR0 is set The RQ0R and RQ0RR b...

Page 841: ...t queue entry in Receive Queue 0 PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na...

Page 842: ...Q1R and SQ1RR bits in the SQCR1 will be reinitialized along with the Put Get Pointers 30 02 Send Queue 1 Reset Request SQ1RR The other processor is requesting that Send Queue 1 be reinitialized by ret...

Page 843: ...na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na Attribute L...

Page 844: ...ssages have been added to Receive Queue 1 Table 524 Receive Queue Put Get Pointer Register 1 RQPG1 Bit Default Description 31 16 0000H Receive Queue 1 Get Pointer Index of the next queue entry to read...

Page 845: ...ssor The RQ1R and RQ1RR bits in the RQCR1 will be reinitialized along with the Put Get Pointers 30 02 Receive Queue 1 Reset Request RQ1RR The other processor is requesting that Receive Queue 1 be rein...

Page 846: ...12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro...

Page 847: ...r adding new messages Table 528 Send Queue Put Get Pointer Register 2 SQPG2 Bit Default Description 31 16 0000H Send Queue 2 Get Pointer Index of the next queue entry for the other processor to read i...

Page 848: ...Q2R and SQ2RR bits in the SQCR2 will be reinitialized along with the Put Get Pointers 30 02 Send Queue 2 Reset Request SQ2RR The other processor is requesting that Send Queue 2 be reinitialized by ret...

Page 849: ...na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na rw na Attribute L...

Page 850: ...ssages have been added to Receive Queue 2 Table 532 Receive Queue Put Get Pointer Register 2 RQPG2 Bit Default Description 31 16 0000H Receive Queue 2 Get Pointer Index of the next queue entry to read...

Page 851: ...ssor The RQ2R and RQ2RR bits in the RQCR2 will be reinitialized along with the Put Get Pointers 30 02 Receive Queue 2 Reset Request RQ2RR The other processor is requesting that Receive Queue 2 be rein...

Page 852: ...12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro...

Page 853: ...r adding new messages Table 536 Send Queue Put Get Pointer Register 3 SQPG3 Bit Default Description 31 16 0000H Send Queue 3 Get Pointer Index of the next queue entry for the other processor to read i...

Page 854: ...turning the Put Get pointers to their default values Note Reinitialization of Send Queue 3 is not effective until Send Queue 3 Reset bit SQ3R in SQCR3 is set SQ3R and SQ3RR bits in SQCR3 are reinitial...

Page 855: ...ss for the first queue entry in Send Queue 3 PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na rv na...

Page 856: ...turning the Put Get pointers to their default values Note The reinitialization of Receive Queue 3 will not take effect until the Receive Queue 3 Reset bit RQ3R in the RQCR3 is set The RQ3R and RQ3RR b...

Page 857: ...ister 3 RQUBAR3 Bit Default Description 31 4 00000000H Reserved 3 0 0H Receive Queue 3 Base Upper Base Address The upper 4 bits of the address for the first queue entry in Receive Queue 3 PCI IOP Attr...

Page 858: ...ponding bit in the IMUTSRx register When an Intel XScale processor reads an IMUTSRx register and both bits are cleared the value returned to the Intel XScale processor will be the current value of the...

Page 859: ...g endian mode the IMU would dynamically byte swap the aligned DWORD within which the data byte is contained Refer to Figure 120 Otherwise if the Intel XScale processor is running in little endian mode...

Page 860: ...fect to this bit Note Both bits 1 and 0 cannot be 112 at any given time 00 02 Intel XScale processor 0 bit This bit is only affected by Intel XScale processor 0 transactions and is a read only bit for...

Page 861: ...em to relay status and reliability information of the 81341 and 81342 to the system The SMBus Interface Unit is a peripheral device that resides on a 81341 and 81342 internal bus Data is transmitted t...

Page 862: ...e SMBus address is set upon P_RST by sampling the Peripheral Bus Interface Reset Strap inputs A 16 13 When the pins are sampled the resulting 81341 and 81342 address is stored in the Reset Strap Statu...

Page 863: ...The SMBus master can then initiate a read sequence which returns the status of the internal read or write command and also the data in case of a read Each SMBus transaction has an 8 bit command driven...

Page 864: ...Address Register PMMRBAR Refer to the Peripheral Registers Chapter for more details on the PMMRBAR register description The 81341 and 81342 ignores the upper 5 bits of ADDR2 and the entire ADDR3 field...

Page 865: ...are the received address with their own and the target slave finds a match The next data bit from the initiator indicates the transfer direction A value of 1 indicates that the target needs to transfe...

Page 866: ...CK requires SMBDAT 1 during SMBCLK 1 as shown below During a write cycle the 81341 and 81342 must drive an ACK after the address direction phase and after the data phase During a read cycle the 81341...

Page 867: ...e SMBus access is delayed by stretching Table 547 SMBus Interface Registers for Configuration Space Access Register Name and Function CMD Command BYTCNT Byte Count ADDR3 Bus Numbera a The ADDR3 field...

Page 868: ...he SMBus port are initiated by writing to the Command register While a command is in progress all future writes or reads are NACKed by the 81341 and 81342 to avoid having registers overwritten while i...

Page 869: ...ugh an SMBus write s and later followed by an SMBus read to read the status and the read data For SMBus read transactions the last byte of data or the PEC byte when enabled is NACKed by the master to...

Page 870: ...002US Figure 128 DWORD Memory Read Protocol SMBus Block Write Block Read PEC Enabled Figure 129 DWORD Configuration Read Protocol SMBus Word Write Word Read PEC Enabled Figure 130 DWORD Configuration...

Page 871: ...Read Protocol SMBus Word Write Byte Read PEC Enabled S 11X0_XXX W A Cmd 10110001 A Dest Mem A Add Offset 23 16 A PEC S 11X0_XXX W A Cmd 01110001 A Add Offset 15 8 A P S 11X0_XXX W A Cmd 10110000 Sr 11...

Page 872: ...Write DWord internal command the two least significant bits of the Register Number are ignored This is different from PCI where the byte enables are used to indicate the byte of interest After all th...

Page 873: ...41 and 81342 I O Processors December 2007 Developer s Manual Order Number 315037 002US 873 SMBus Interface Unit Intel 81341 and 81342 Figure 137 DWORD Configuration Write Protocol SMBus Byte Write PEC...

Page 874: ...set then the PEC byte is checked in the slave interface When the check indicates a failure then the slave NACKs the PEC packet and does not issue the command on the internal interface An SMBus master...

Page 875: ...ller ADDR0 Register Number SM_ADDR0 on page 877 Section 557 SMBus Controller Data Register SM_DATA on page 878 Section 558 SMBus Controller Status Register SM_STS on page 878 Table 551 SMBus Controlle...

Page 876: ...d 81342 14 4 4 SMBus Controller ADDR2 Register SM_ADDR2 This register should be programmed with the Device Number and Function Number of the desired configuration register The Status Register should b...

Page 877: ...7 0 of the Register Number of the desired configuration register for 4 KByte configuration space The Status Register should be checked to make sure that there is not a command currently in progress b...

Page 878: ...of data are used The register number must be DWORD aligned The Status Register should be checked to make sure that there is not a command currently in progress before writing to this register Writing...

Page 879: ...time during the functional operation Available status information includes the type and condition of the transfer operations being performed by a UART and any error conditions parity overrun framing o...

Page 880: ...Receiver FIFO CTS input from modem controls UART transmitter Fully programmable serial interface characteristics 5 6 7 or 8 bit characters Even odd or no parity detection 1 1 1 2 or 2 stop bit generat...

Page 881: ...reading of the Modem Status register CTS has no effect on the transmitter The user can program the UART to interrupt the processor when DCTS changes state The programmer can then stall the outgoing d...

Page 882: ...e transition Figure 139 shows the NRZ coding of the data byte 8b 0100 1011 Note that the byte s LSB is transmitted first The unit is disabled upon reset and users need to enable the unit by setting th...

Page 883: ...transmitter FIFO and transmitter interrupt are enabled FCR 0 1 IER 1 1 transmit interrupts occur as follows When the Flow Control Register Transmitter Interrupt Level TIL bit FCR 3 is clear 0 The Tran...

Page 884: ...timer is reset when a character is read from the Receiver FIFO When a time out Interrupt has not occurred the time out timer is reset after a new character is received or after the processor reads the...

Page 885: ...ting both CTS and RTS and half autoflow automating only CTS Full Autoflow is enabled by writing a 1 to bits 1 and 5 of the Modem Control register MCR Auto CTS Only mode is enabled by writing a 1 to bi...

Page 886: ...emote transmitter s actual baud rate differs by more than one percent of its target The table method is more immune to such errors since the table rejects uncommon baud rates and rounds to the common...

Page 887: ...y any divisor from 1 to 216 1 The baud rate generator output frequency is 16 times the baud rate Two 8 bit registers store the divisor in a 16 bit binary format These Divisor Registers must be loaded...

Page 888: ...R UART x FIFO Control write only Base 0CH X UxLCR UART x Line Control R W Base 10H X UxMCR UART x Modem Control R W Base 14H X UxLSR UART x Line Status Read only Base 18H X UxMSR UART x Modem Status R...

Page 889: ...Byte R W 2304H 1 U0DLH UART 0 Divisor Latch High Byte R W 2324H X U0FOR UART 0 FIFO Occupancy Register R W 2328H X U0ABR UART 0 Autobaud Control Register R W 232CH X U0ACR UART 0 Autobaud Count Regis...

Page 890: ...de writing to THR puts data to the top of the FIFO The data at the bottom of the FIFO is loaded to the Shift register when it is empty In eight bit Peripheral mode the 24 most significant bits are ign...

Page 891: ...t is enabled 5 02 NRZ coding Enable NRZE 0 NRZ coding disabled 1 NRZ coding enabled 4 02 Receiver Time Out Interrupt Enable RTOIE 0 Receiver data Time out Interrupt disabled 1 Receiver data Time out I...

Page 892: ...ication register IIR stores information indicating that a prioritized interrupt is pending and the source of that interrupt Table 567 UART x Interrupt Identification Register UxIIR Bit Default Descrip...

Page 893: ...tting RESETRF bit in FCR register TOD 1 1 0 0 Second Highest Character Timeout indication FIFO Mode only At least 1 character is in receiver FIFO and there was no activity for a time period Reading th...

Page 894: ...bits are set in the IIR 00 1 byte or more in FIFO causes interrupt 01 8 bytes or more in FIFO causes interrupt 10 16 bytes or more in FIFO causes interrupt 11 32 bytes or more in FIFO causes interrup...

Page 895: ...ter the FIFO is cleared RESETRF is automatically reset to 0 0 no effect 1 The receiver FIFO is cleared FIFO counter set to 0 After clearing bit is automatically reset to 0 0 02 Transmit and Receive FI...

Page 896: ...ic In FIFO mode wait for the transmitter to be idle TEMT 1 to set and clear the break bit 0 no effect on TXD output 1 forces TXD output to 0 space 5 02 Sticky Parity STKYP Can be used in multiprocesso...

Page 897: ...STB is clear 0 one stop bit is generated in the transmitted data When STB is set 1 when a 5 bit word length is selected via WLS 1 0 then 1 and one half stop bits are generated When STB is set 1 when...

Page 898: ...is activated by MCR bit 1 instead of the modem control input A Break signal can also be transferred from the transmitter section to the receiver section in Loop Back mode When LOOP is set 1 the follow...

Page 899: ...R is set auto RTS is enabled RTS behaves as follows Auto RTS disabled Autoflow works only with auto CTS Auto RTS enabled Autoflow works with both auto CTS and auto RTS 0 02 Reserved Table 571 UART x M...

Page 900: ...after the previous bytes are read and the erroneous byte is moved to the bottom of the FIFO Table 572 UART x Line Status Register UxLSR Sheet 1 of 3 Bit Default Description 31 8 00 0000h Reserved 7 02...

Page 901: ...ondition BI shows the Break condition for the character at the bottom of the FIFO not the most recent character received 0 No break signal has been received 1 Break signal has been received 3 02 Frami...

Page 902: ...w condition and reset when the processor reads the Line Status register 0 No overflow error Data has not been lost 1 Overflow error Receive data has been lost 0 02 Data Ready DR Set to a logic 1 when...

Page 903: ...le Register is set Table 574 UART x Modem Status Register UxMSR Bit Default Description 31 5 000 0000h Reserved 4 02 Clear to Send CTS This bit is the complement of the Clear to Send CTS input This bi...

Page 904: ...Description 31 8 00 0000h Reserved 7 0 00h No effect on UART functionality P C I I O P A t t r i b u t e s A t t r i b u t e s 28 24 20 16 12 8 4 0 31 rv na rv na rv na rv na rv na rv na rv na rv na...

Page 905: ...egister UxDLH Bit Default Description 31 8 00 0000h Reserved 7 0 00h High byte compare value to generate baud rate P C I I O P A t t r i b u t e s A t t r i b u t e s 28 24 20 16 12 8 4 0 31 rv na rv...

Page 906: ...for each byte of data written to the Receive FIFO and decremented once for each byte read Table 578 UART x FIFO Occupancy Register UxFOR Bit Default Description 31 7 000 0000h Reserved 6 0 000 00002...

Page 907: ...processor to read the Auto Baud Count register ACR and determine the baud rate using its own algorithm rather than using the UARTs 0 Software programs Divisor Latch Registers 1 UART Programs Divisor...

Page 908: ...t value into the ACR The value is written regardless of the state of the auto baud UART program bit Table 580 UART x Auto Baud Count Register UxACR Bit Default Description 31 16 0000h Reserved 15 0 00...

Page 909: ...rporation consisting of a two pin interface SDA is the data pin for input and output functions and SCL is the clock pin for reference and control of the I2 C bus The I2 C bus allows the 81341 and 8134...

Page 910: ...ses an EEPROM as a slave to receive data The 81341 and 81342 is a master transmitter and the EEPROM is a slave receiver When the 81341 and 81342 reads data the 81341 and 81342 is a master receiver and...

Page 911: ...o the SCL line The I2 C bus serial operation uses an open drain wired AND bus structure which allows multiple devices to drive the bus lines and to communicate status about events such as arbitration...

Page 912: ...ure 141 shows a block diagram of the I2 C Bus Interface Unit and its interface to the internal bus The I2 C Bus Interface Unit consists of the two wire interface to the I2 C bus an 8 bit buffer for pa...

Page 913: ...data buffer that receives a byte of data from the shift register interface of the I2 C bus on one side and parallel data from the 81341 and 81342 internal bus on the other side The serial shift regist...

Page 914: ...5 Slave Operations on page 925 When the 81341 and 81342 wants to initiate a read or write on the I2 C bus the I2 C Bus Interface Unit transitions from the default Slave Receive mode to Master Transmit...

Page 915: ...s sent by the I2C Bus Interface Unit This is used when multiple data bytes need to be transferred 0 1 STARTCondition and Repeated START The I2C Bus Interface Unit sends a START condition and transmit...

Page 916: ...s used in master transmit mode while the 81341 and 81342 is transmitting multiple data bytes see Figure 142 Software writes the data byte sets the IDBR Transmit Empty bit in the ISR and interrupt when...

Page 917: ...nd the I2 C unit passes this onto the serial bus when the Transfer Byte bit in the ICR is set See Section 16 8 1 I2C Control Register x ICRx When the I2 C unit is in transmit mode master or slave 1 So...

Page 918: ...g the Ack and the addressed slave device transitions to slave transmit mode When a Nack is returned the I2 C unit aborts the transaction by automatically sending a STOP and setting the ISR bus error b...

Page 919: ...ror detected bit in the ISR is not set for a master receive mode Nack as required by the I2 C bus protocol The I2 C unit automatically transmits the Ack pulse based on the Ack Nack ICR bit after recei...

Page 920: ...tion Each master on the I2 C bus generates its own clock on the SCL line for data transfers With masters generating their own clocks clocks with different frequencies may be connected to the SCL line...

Page 921: ...sing the 81341 and 81342 as a slave device the I2 C unit switches to slave receive mode and the original data in the I2 C data buffer register is overwritten Software is responsible for clearing the s...

Page 922: ...Performed after the target slave address and the R W bit are in the IDBR Intel XScale processor sets the START bit Intel XScale processor sets the Transfer Byte bit which initiates the start conditio...

Page 923: ...STOP When the Ack Nack Status bit is set indicating Nack Transfer Byte bit is clear but the STOP bit is clear then the Intel XScale processor has two options 1 set the START bit write a new target add...

Page 924: ...Data Chaining see Figure 149 Figure 150 shows the wave forms of SDA and SCL for a complete data transfer Figure 148 Master Receiver Read from Slave Transmitter Figure 149 Master Receiver Read from Sl...

Page 925: ...n interrupt is signalled when enabled after the matching slave address is received and acknowledged Read one byte of I2C Data from the IDBR Slave receive only Data receive mode of I2C slave operation...

Page 926: ...o Slave Transmitter Repeated START Master Transmitter Write to Slave Receiver Master to Slave Slave to Master START Slave Address R W 0 ACK Data Byte ACK Data Byte STOP N Bytes ACK Write ACK First Byt...

Page 927: ...es a general call address and the ICR General Call Disable bit is clear the I2 C unit Sets the ISR general call address detected bit Sets the ISR slave address detected bit Interrupts when enabled the...

Page 928: ...rupt Read ISR Unit Busy clear Slave STOP Detected set 7 Clear interrupt by clearing Slave STOP Detected Interrupt bit 16 4 3 Read 2 Bytes as a Slave 1 Wait for Slave Address Detected interrupt Read IS...

Page 929: ...ess 5 Wait for Buffer empty interrupt When interrupt arrives Note Unit is sending STOP Read status register IDBR Transmit Empty set Unit busy set maybe R W bit clear Clear IDBR Transmit Empty Interrup...

Page 930: ...r STOP bit Set Transfer Byte bit to initiate the access 7 Wait for Buffer empty interrupt Read status register IDBR Transmit Empty set Unit busy set R W bit clear Clear IDBR Transmit Empty bit to clea...

Page 931: ...the access 5 Wait for Buffer full interrupt Read status register IDBR Receive Full set Unit busy set R W bit Set Ack Nack bit Clear Clear IDBR Receive Full bit to clear the interrupt Read IDBR data 6...

Page 932: ...is set only the 81341 and 81342 I2C unit resets the associated I2C MMRs remain intact When resetting the I2C unit with the ICRx unit reset use the following guidelines 1 In the ICRx register set the...

Page 933: ...r the I2C unit generated a Nack pulse Note Software is responsible for insuring that misplaced START and STOP conditions do not occur See Section 16 6 Glitch Suppression Logic on page 932 09 02 IDBR R...

Page 934: ...low inserting wait states until the Transfer Byte bit is set 02 02 Ack Nack Control defines the type of Ack pulse sent by the I2C unit when in master receive mode 0 The I2C unit sends an Ack pulse af...

Page 935: ...actions continue Software must insure that misplaced START and STOP conditions do not occur See Section 16 3 3 Arbitration on page 920 09 02 Slave Address Detected 0 No slave address detected 1 I2C un...

Page 936: ...unit received or sent an Ack on the bus 1 The I2C unit received or sent a Nack This bit is used in slave transmit mode to determine when the byte transferred is the last one This bit is updated after...

Page 937: ...rals that might exist in the system The ISAR is not affected by the 81341 and 81342 being reset The ISAR register default value is 00000002 Table 590 I2C Slave Address Register x ISARx Bit Default Des...

Page 938: ...e the I2C bus is ready to transfer the next byte packet the I2C Bus Interface Unit inserts wait states until the Intel XScale processor writes the IDBRx and sets the Transfer Byte bit When the I2C Bus...

Page 939: ...Register x IBMRx Bit Default Description 31 02 0 Reserved 01 1 SCL Status This bit continuously reflects the value of the SCL pin 00 1 SDA Status This bit continuously reflects the value of the SDA pi...

Page 940: ...x Bit Default Description 31 03 0 Reserved 02 0 SDA Control When bit 0 of the IMBCRx is set this bit controls the SDA pin 0 Pull Down the SDA pin 1 Do Not Pull Down the SDA pin 01 0 SCL Control When b...

Page 941: ...programming the INTCTL 3 0 registers 17 1 2 General Purpose Outputs The output function of the GPIO pins is controlled by two registers as stated in Section 17 2 3 GPIO Output Data Register GPOD on p...

Page 942: ...rough the internal memory bus Each is a 32 bit register and is memory mapped in the Intel XScale processor memory space The programmer interface to the General Purpose I O is through memory mapped con...

Page 943: ...ed onto the GPIO 10 pin 09 12 GPIO9 Output Enable When clear bit 9 of the GPIO Output Data Register is enabled onto the GPIO 9 pin 08 12 GPIO8 Output Enable When clear bit 8 of the GPIO Output Data Re...

Page 944: ...11 GPIO 11 during P_RST assertion GPIO11 Input Data This bit reflects the state of the GPIO 11 pin 10 GPIO 10 during P_RST assertion GPIO10 Input Data This bit reflects the state of the GPIO 10 pin 09...

Page 945: ...state of the GPIO 2 pin 01 GPIO 1 during P_RST assertion GPIO1 Input Data This bit reflects the state of the GPIO 1 pin 00 GPIO 0 during P_RST assertion GPIO0 Input Data This bit reflects the state o...

Page 946: ...register is cleared 08 02 GPIO8 Output Data This bit value is driven on the GPIO 8 pin when bit 8 of the GPOE register is cleared 07 02 GPIO7 Output Data This bit value is driven on the GPIO 7 pin wh...

Page 947: ...rs Each counter has a corresponding command event status and data register The PMON unit implements eight counters Signals representing events from throughout the chip are routed to the PMON unit Soft...

Page 948: ...02US 18 2 1 Clock Counter Control When a counter is sampled the current value of the counter is latched into the corresponding data register The command event status and data registers are accessible...

Page 949: ...ted by the PMON unit This includes clock crossing logic Two optional external pins allow for external visibility and control of the counters The output pin signals that one of the following conditions...

Page 950: ...unters is not intended to be any wider than 32 bits This means that all registers are accessed one at a time All of the following examples assume starting with an idle system all counters stopped and...

Page 951: ...ing the system and allowing the software to read data registers or do whatever else may be desired Example 17 Simple Counting This example demonstrates how to measure the number of times event A occur...

Page 952: ...rt stop sample and other commands to be executed as a result of other events happening Command Triggers refers to the ability of a command to be issued to the PMON unit and have it not be executed unt...

Page 953: ...ould no longer be counted Example 18 How many Event A s happen before the first Event B is detected This example demonstrates how to measure the number of times event A occurs before the first occurre...

Page 954: ...up to 2N 1 each clock tick where N is the number of counters available For example with 8 counters we could track an increment decrement of up to 128 27 each clock This would be done by assigning an...

Page 955: ...seful when it is presented in a histogram Example 20 on page 956 outlines the command sequences required to generate such a histogram See the Head of Queue Histogram example in another section for mor...

Page 956: ...of a particular queue No block diagram for this example Table 601 Queue Depth Histogram Example Opcode Target Counter Increment Event Decrement Event Trigger Event Write Threshold bucket size in Data...

Page 957: ...ent takes place An alternative way to represent the data in the preceding table is as follow For X 1 to 3 Write Threshold bucket size X into Data Register 0 Write Event Register 0 Increment QueueNotEm...

Page 958: ...Intel 81341 and 81342 PMON Unit Intel 81341 and 81342 I O Processors Developer s Manual December 2007 958 Order Number 315037 002US Figure 163 Block Diagram of HOQ Histogram Example B6304 01...

Page 959: ...Intel 81341 and 81342 I O Processors December 2007 Developer s Manual Order Number 315037 002US 959 PMON Unit Intel 81341 and 81342 Figure 164 Waveforms of HOQ Histogram Example B6305 01...

Page 960: ...es identical queue behavior but the Counter 1 value called Condition Code Matches below differs due to having a different threshold value each time The condition code match values 10 8 4 3 from the 4...

Page 961: ...oduce the correct count Any events from different frequency domains must be preconditioned to assure count accuracy measured For these clock domain crossing signals 95 accuracy is sufficient over a 1...

Page 962: ...are located in the PMON Feature Enable Register PMONEN on page 964 18 5 2 2 Interrupt Output An internal interrupt is delivered to the Interrupt Control Unit when Interrupts are enabled in the PMON Fe...

Page 963: ...Table 603 PMON Internal Bus Memory Mapped Register Range Offsets on page 963 to the Register Offset Table 604 PMON Register Summaries on page 963 For example the offset to PMMRBAR of the PMON Status...

Page 964: ...les 81341 and 81342 PMON unit generated interrupts PCI IOP Attributes Attributes 28 24 20 16 12 8 4 0 31 rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv...

Page 965: ...re specified as a relative offset to a 512KB aligned global PMMR offset The default for the 512KB aligned offset is 0 FFD8 0000H defined by the PMMRBAR register See also Chapter 21 0 Peripheral Regist...

Page 966: ...h PMON Data Register 2 PMON_DATA2 030h PMON Command Register 3 PMON_CMD3 034h PMON Event Register 3 PMON_EVR3 038h PMON Status Register 3 PMON_STS3 03Ch PMON Data Register 3 PMON_DATA3 040h PMON Comma...

Page 967: ...verflow Underflow Indicator Enable OUIE 0 No indication provided when a counter overflow or underflow occurs except for setting the Overflow Underflow Indicator OUI status bit 1 When the overflow unde...

Page 968: ...Not Equal 110 Less Than or Equal 111 True always generate threshold event 20 0b Select ALL Counters SAC This bit controls how the opcode in bits 19 16 is applied to all counters The rest of the PMON_C...

Page 969: ...register 0101 Restart The corresponding counter resets then starts counting again This is essentially a Reset Start command This functionality facilitates generating histograms by allowing an event t...

Page 970: ...to be re executed every time the trigger is detected Refer to the Event tables for valid values For the Stop Start and Reset opcodes re executing every time the trigger is detected is meaningless For...

Page 971: ...rom SAS SATA Port 1 etc 27 16 000h Decrement Event DE This field contains Event Selection Code ESC that the unit is required to detect before decrementing the associated counter This field is only app...

Page 972: ...poll this bit until it reads a 0 and then owns the usage of the corresponding counter This bit has no other effect on any PMON Counter registers and is only used as a semaphore among various independe...

Page 973: ...000h Reserved 11 4 TBD Clock Period CP This fixed point field is 5 3 format which allows representing clock periods from 0 125 ns 8 GHz to 31 875 ns a little over 31 MHz in 125 ps increments Example 1...

Page 974: ...r of clock ticks or occurrences contained in PMON event counter n at time of sampling The register is programmed to contain the threshold value that is compared to the value in the event counter when...

Page 975: ...8 5 7 1 Null Event The Null Event is not an actual event When used as an increment or decrement event no action takes place When used as Command Trigger it causes command to be triggered immediately a...

Page 976: ...threshold event the threshold event triggers another counter to stop counting event AAAh 18 5 7 3 Threshold Events These are the outputs of the threshold comparators When the value in a data register...

Page 977: ...ng table represents the Source Select Field values for each port Note The ADMA is a requester on the South Internal Bus for PCI data transfers as well as descriptor fetches descriptor status writes CR...

Page 978: ...could occur 409 reserved 40A ECC Soft Error Corrections N O of single bit DDR SDRAM Memory ECC errors corrected per 16 byte quanta PMON 40B Waiting on Memory Refresh N OD Reads or Writes waiting behin...

Page 979: ...request queue has one or more entries 1 of 2 signals required to generate a Head of Queue Histogram for this queue 487 DM Read Request Queue Full Ya OD DDR SDRAM Memory controller read request queue...

Page 980: ...rite transactions with coherent hits with a single read transaction 491 DM Write Coherent Hits Y O of hits in this port s read request queue for coherency conflicts from a write transactions in the me...

Page 981: ...688 PCI Out bound Data Transferred N D Count equals number of 8_byte data cycles actual data transferred can be 1 to 8 bytes Data transferred for all cases where I O Processor is initiator of transact...

Page 982: ...ets Transmitted including Flow Control Updates 713 Total DLLPs Received N O Data Link Layer Packets Received including Flow Control Updates 714 71F Reserved 720 Inbound Data Transferred N OD 721 Inbou...

Page 983: ...eSelect Value Port 0 Intel XScale core 0 1 Intel XScale core 1 2 Internal Bus Bridge 3 7 Reserved Table 622 North Internal Bus Initiator Events Event Selection Code Event SRC Type Comment 800 NIB Addr...

Page 984: ...South Internal Bus Source Select Summary Source Select Value Port 0 ATU E 1 ATU X 2 Internal Bus Bridge 3 Reserved 4 ADMA 2 0 a a A breakdown of the individual ADMA channel activity can be found in th...

Page 985: ...gions 3 4 and 6 are driven off the core PLL and are pseudo synchronous to each other There are asynchronous boundaries between regions 1 3 regions 2 3 6 3 and between regions 7 3 Figure 168 Intel 8134...

Page 986: ...og front end for this region generates the 2 5 GHz clock used for the serial PCI Express interface as well as a 250 MHz clock used by the transaction layer In addition to the locally generated clocks...

Page 987: ...iona a 81341 and 81342 does not support PCI X 533Mhz P_PCIXCAP P_MODE2 P_M66EN PCIXM1_100 PCIXM2_100 PCI Bus Mode PCI Bus Frequency ATUX PCSR 19 16 0 11VCC b b A in table indicates value is a don t ca...

Page 988: ...zation Pattern1 PERR DEVSEL STOP TRDY ATUX PCSR 19 16 Mode Clock Frequency MHz Minimum Maximum Deasserted Deasserted Deasserted Deasserted 1111 PCI 33 16 33 1111 PCI 66 33 66 Deasserted Deasserted Dea...

Page 989: ...to drive the ATUX PCI interface These clock outputs are can only be used when the PCI Express reference clock REFCLK is used as the primary chip clock and the ATUX is enabled and configured to operate...

Page 990: ...d for low speed peripheral units Currently this includes I2 C bus interface General Purpose I O unit UART serial bus interface Region 5 contains an output clock SCL used for the I2 C bus interface The...

Page 991: ...n 19 1 1 2 4 Secondary Clock Outputs on page 989 for more details P_CLKO 3 0 Output PCI Bus Output Clocks When REFCLKN REFCLKP are used the I O processor can generate the PCI output clocks These pins...

Page 992: ...01 Reserved 10 DDR II SDRAM 533 MHz 11 DDR II SDRAM 400 MHz default PCIXM1_100 Strap PCI X Mode 1 100 MHz Enable When operating as the Central Resource PCIX_EP 1 this strap limits the PCI X bus to 100...

Page 993: ...s not applicable when the PCI Express interface is disabled A subset of straps are sampled as described in Section 19 5 Reset Strapping Options PCI Express Loopback When operating as an endpoint and t...

Page 994: ...ale processor to imitate a reset to another core in the system including itself 19 2 3 Secondary Bus Reset When operating as a root complex or central resource the following secondary bus resets apply...

Page 995: ...et The PCI Express specification defines an in band reset sequence that is used to reset the link and downstream components The Root Complex communicates the fact that it is entering and coming out of...

Page 996: ...e of the fundamental resets and control the default value of the Core Processor Reset bits in function 0 When invoked via the strap software should clear the Core Processor Reset bits in function 0 to...

Page 997: ...raffic before initiating the Internal Bus Reset 1 Disable the ATU from either claiming or initiating new transactions by clearing the Bus Master Enable and the Memory Enable in the ATU Command Registe...

Page 998: ...X or the target the ATUX no longer requests the PCI bus In PCI X mode the ATUX allows any outstanding split completions due to prior outstanding Split Requests to Master Abort on the PCI Bus Since the...

Page 999: ...ss link is a point to point interface so no precautions need to be taken before resetting the link End Point Mode No affect on ATUE logic All ATUX Configuration Registers retain their current values R...

Page 1000: ...signal while the P_RST pin can be tied to the system power good signal When the sticky bit functionality is not required the WARM_RST pin should not be used and must be tied to Vcc When the PCI Expre...

Page 1001: ...cember 2007 Developer s Manual Order Number 315037 002US 1001 Clocking and Reset Intel 81341 and 81342 19 4 Device Function Select In all cases the INTERFACE_SEL_PCIX strap affects whether the part op...

Page 1002: ...mple all straps at the deassertion of both P_RST and WARM_RST PCI Express Hot Reset Loopback Disable Link and Link Down When operating as a PCI Express endpoint the following straps are re sampled at...

Page 1003: ...oftware clears the Core 1 Processor Reset bit 0 Hold in reset Requires pull down resistor 1 Don t hold in reset Default mode MEM_FREQ 1 0 Memory Frequency Determines the frequency of the DDR2 SDRAM me...

Page 1004: ...h and when PCIX_32BIT is deasserted REQ64 is driven low 0 32 Bit PCI X Bus Requires pull down resistor 1 64 Bit PCI X Bus Default mode HS_SM Hot Swap Startup Mode 0 Hot Swap Mode Enabled Requires pull...

Page 1005: ...20 1 Overview This chapter summarizes testability and configuration features incorporated in the Intel 81341 and 81342 I O Processors 81341 and 81342 The test and control logic is based on the IEEE 11...

Page 1006: ...controller Instruction register Group of test data registers Each of these is described in more detail below Figure 169 shows a generic diagram for logic conforming to the IEEE 1149 1 test standard F...

Page 1007: ...ising edge of TCK Data shifted from TDI through a register to TDO appears non inverted at TDO after a number of rising and falling edges of TCK determined by the length of the instruction or test data...

Page 1008: ...gic instruction register data registers etc occur on either rising or falling edge of TCK as show in Figure 170 See the description of each state to learn which For greater detail on the state machine...

Page 1009: ...oller remains in this state as long as TMS is held low In the Run Test Idle state activity in selected test logic occurs only when certain instructions are present For example the RUNBIST instruction...

Page 1010: ...DR state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO All test data registers selected by the current inst...

Page 1011: ...is connected between TDI and TDO and shifts data one bit position nearer to its serial output on each rising edge of TCK All test data registers selected by the current instruction retain their previ...

Page 1012: ...er enters the Update IR state and the scanning process terminates When TMS is held low during the next rising edge of TCK the controller re enters the Shift IR state 20 2 2 16 Update IR State The inst...

Page 1013: ...chine outputs are decoded to select and control the test data register selected by that instruction Upon latching all actions caused by any previous instructions must terminate On activation of TRST t...

Page 1014: ...interfering with that normal operation The instruction causes Boundary Scan register cells associated with outputs to sample the value being driven by or to the processor When the TAP controller is in...

Page 1015: ...er provides the shortest path between TDI and TDO This path can be selected when no test operation is being performed While the Bypass Register is selected data is transferred from TDI to TDO without...

Page 1016: ...continues to operate with the bypass register connected between TDI and TDO The part may have other settings as long as they do not interfere with these two requirements Following the use of High Z th...

Page 1017: ...the Each of these peripherals fully describe the independent functionality of the registers control and usage Control and status registers for the Intel XScale processor use the CCR interface Accesse...

Page 1018: ...d of the instruction denotes the register number to be accessed The opcode_1 and opcode_2 fields of the instruction should be zero The CRm field must be set to 0 for the Interrupt Controller Unit and...

Page 1019: ...ough 0 FFDF FFFFH The Messaging Unit occupies 8 KBytes of space and is located at addresses 0 FF00 0000H through 0 FF00 1FFFH The ATU X Outbound I O Translation Window occupies 64 KBytes of space and...

Page 1020: ...H 0 FFFE 0000H 0 FFD4 0000H 0 FFD2 0000H 0 FFCF C000H ATU E Outbound I O Translation Window ATU X Outbound I O Translation Window Default Default Range 0 FFF0 0000H Reserved 0 FFF8 0000H Reserved 0 FF...

Page 1021: ...D8 0000H Code Data External Memory 0 FFFD 0000H Default Range 0 FFFB 0000H 0 FFE0 0000H Internal SRAM Memory Default Range 0 FFCF C000H ATU E Outbound I O Translation Window ATU X Outbound I O Transla...

Page 1022: ...81341 and 81342 architecture and software must not access these related registers and resources until software can ensure that the Base Address Register has truly been updated Refer to the Intel XSca...

Page 1023: ...d 4 1000H through 4 1FFFH 4 KBytes Reserved 4 2000H through 4 2FFFH 4 KBytes Reserved 4 3000H through 4 3FFFH 4 KBytes Reserved 4 4000H through 4 4FFFH 4 KBytes Reserved 4 5000H through 4 5FFFH 4 KByt...

Page 1024: ...6 9FFFH 8 KBytes Not Claimed by any Unit 6 A000H through 6 BFFFH 8 KBytes Not Claimed by any Unit 6 C000H through 6 DFFFH 8 KBytes Not Claimed by any Unit 6 E000H through 6 FFFFH 8 KBytes Reserved 7 0...

Page 1025: ...Base Address Offset ADMA Channel Control Register x ACCRx 32 000 ADMA Channel Status Register x ACSRx 32 004 ADMA Descriptor Address Register x ADARx 32 008 Reserved x 00C through 014 Internal Interf...

Page 1026: ...er 9_x SUAR9_x 32 088 Source Lower Address Register 10_x SLAR10_x 32 08C Source Upper Address Register 10_x SUAR10_x 32 090 Source Lower Address Register 11_x SLAR11_x 32 094 Source Upper Address Regi...

Page 1027: ...rtion Register DBAR 32 10H Door Bell Enable Other Processor Register DBEOR 32 14H Reserved 32 18H Reserved 32 1CH Send Queue Put Get Pointer Register 0 SQPG0 32 20H Send Queue Control Register 0 SQCR0...

Page 1028: ...egister 3 SQPG3 32 80H Send Queue Control Register 3 SQCR3 32 84H Send Queue Lower Base Address Register 3 SQLBAR3 32 88H Send Queue Upper Base Address Register 3 SQUBAR3 32 8CH Receive Queue Put Get...

Page 1029: ...500H Table 644 SRAM Memory Controller Register Description Name Registe r Sizein Bits Internal Bus Address Offset Relative to SMCU Base Address Offset SRAM Base Address Register SRAMBAR 32 00H SRAM Up...

Page 1030: ...s Offset Register Offset Table 645 PBI Base Address Offset Unit PBI Base Address Offset Relative to PMMRBAR PBI 1580H Table 646 Peripheral Bus Interface Unit Register Description Name Register Size in...

Page 1031: ...idge Address Offset Register Offset Table 649 Internal Bus Bridge Base Address Offset Unit Internal Bus Bridge Base Address Offset Relative to PMMRBAR Internal Bus Bridge 1780H Table 650 Internal Bus...

Page 1032: ...00CH SDRAM Upper Base Register SDUBR 32 010H SDRAM Bank Size Register SBSR 32 014H SDRAM 32 bit Region Size Register S32SR 32 018H DDR ECC Control Register DECCR 32 01CH DDR ECC Log 0 Register DELOG0...

Page 1033: ...te the actual register address Internal Bus Address PMMRBAR I O Pad Control Base Address Offset Register Offset Note DCAL and DQS registers are described in the DDR SDRAM Memory Controller Unit and th...

Page 1034: ...ock Register 0 DLLR0 32 1CH DLL Delay for DQS2 DQS2 DQS3 and DQS3 Clock Register 1 DLLR1 32 20H DLL Delay for DQS4 DQS4 DQS5 and DQS5 Clock Register 2 DLLR2 32 24H DLL Delay for DQS6 DQS6 DQS7 and DQS...

Page 1035: ...8H Reserved 32 0CH Reserved 32 10H Unique ID Register 0 UID0 32 14H Unique ID Register 1 UID1 32 18H Reserved x 1CH through 7FH Table 654 I O Pad Control Unit Sheet 2 of 2 Unit Register Description Na...

Page 1036: ...340H Table 656 UART Register Description Name Register Size in Bits Internal Bus Address Offset Relative to UARTx Base Address Offset UART x Receive Buffer Register Read Only DLAB 0 32 00H UART x Tran...

Page 1037: ...l Bus Address PMMRBAR I2 C Base Address Offset Register Offset Table 657 GPIO Offset Unit GPIO Base Address Offset Relative to PMMRBAR GPIO 2480H Table 658 GPIO Register Description Name Register Size...

Page 1038: ...20H Inbound Interrupt Status Register IISR 32 024H Inbound Interrupt Mask Register IIMR 32 028H Outbound Doorbell Register ODR 32 02CH Outbound Interrupt Status Register OISR 32 030H Outbound Interrup...

Page 1039: ...X Table Message Vector Control Register 3 M_MT_MVCR3 32 103C MU MSI X Table Message Address Register 4 M_MT_MAR4 32 1040 MU MSI X Table Message Upper Address Register 4 M_MT_MUAR4 32 1044 MU MSI X Tab...

Page 1040: ...D1 32 10H PMON Event Register 1 PMON_EVR1 32 14H PMON Status Register 1 PMON_STS1 32 18H PMON DATA Register 1 PMON_DATA1 32 1CH PMON Command Register 2 PMON_CMD2 32 20H PMON Event Register 2 PMON_EVR2...

Page 1041: ...ed during reset The PCI Function number associated with each unit and its Base Address Offset are detailed in Table 665 PCI Function MMR Locations Table 665 PCI Function MMR Locations PCI Function Num...

Page 1042: ...ligned Internal Bus Memory Mapped Register Range Offset Table 666 81341 and 81342 ATUX Configuration Space Base Address Offset on page 1042 to the Register Offset Table 667 Address Translation Unit Re...

Page 1043: ...r ASVIR 16 02CH ATU Subsystem ID Register ASIR 16 02EH Expansion ROM Base Address Register ERBAR 32 030H ATU Capabilities Pointer Register ATU_Cap_Ptr 8 034H Reserved 24 035H Reserved 32 038H ATU Inte...

Page 1044: ...ble_Offset 32 0B4H MSI X Pending Bit Array Offset Register MSI X_PBA_Offset 32 0B8H MU MSI X Control Register x MMCRx 32 0BCH Reserved x 0C0H through 0CFH PCI X Capability Identifier Register PCI X_Ca...

Page 1045: ...t Memory Window Translate Value Register 3 OUMWTVR3 32 324H Reserved 32 328H Reserved 32 32CH Outbound Configuration Cycle Address Register OCCAR 32 330H Outbound Configuration Cycle Data Register OCC...

Page 1046: ...ffset Table 668 81341 and 81342 ATUE Configuration Space Base Address Offset on page 1046 to the Register Offset Table 669 Address Translation Unit Registers ATUE on page 1047 For example when INTERFA...

Page 1047: ...ubsystem ID Register ASIR 16 02EH Expansion ROM Base Address Register ERBAR 32 030H ATU Capabilities Pointer Register ATU_Cap_Ptr 8 034H Reserved 24 035H Reserved 32 038H ATU Interrupt Line Register A...

Page 1048: ...H MSI X Pending Bit Array Offset Register MSI X_PBA_Offset 32 0B8H MU MSI X Control Register x MMCRx 32 0BCH Reserved x 0C0H through 0CFH PCI Express Capability Identifier Register PCIE_CAPID 8 0D0H P...

Page 1049: ...24 200H through 25CH Reserved x 260H through 2FFH Outbound I O Base Address Register OIOBAR 32 300H Outbound I O Window Translate Value Register OIOWTVR 32 304H Outbound Upper Memory Window Base Addre...

Page 1050: ...egister OVMPR 32 370H Reserved x 374H through 37FH PCI Interface Error Control and Status Register PIE_CSR 32 380H PCI Interface Error Status PIE_STS 32 384H PCI Interface Error Mask PIE_MSK 32 388H P...

Page 1051: ...I O Processor PCI Function Visibility Configurations cycles that target 81341 and 81342 are translated into memory cycles on the internal bus and access the PCI Attributes section of the PMMR region...

Page 1052: ...f 16 coprocessors each of which can contain up to 256 32 bit registers For completeness the coprocessor space reserved by the ARM Architecture Reference Manual is shown Note All accesses to CP6 unimpl...

Page 1053: ...Register 1 Register 9 Inbound MSI Interrupt Pending Register 2 Register 10 Inbound MSI Interrupt Pending Register 3 Register 11 Undefined Register 12 through Register 15 I n t e r r u p t C o n t r o...

Page 1054: ...r 3 Register 3 Undefined Register 4 15 FIQ Interrupt Source Register 0 7 Register 0 FIQ Interrupt Source Register 1 Register 1 FIQ Interrupt Source Register 2 Register 2 FIQ Interrupt Source Register...

Page 1055: ...n it L2 Cache and BIU Error Logging Register CP7 2 Register 0 L2 Cache and BIU Error Lower Address Register Register 1 L2 Cache and BIU Error Upper Address Register Register 2 Undefined Register 3 15...

Page 1056: ...trol Registers Register 1 Translation Table Base Register Register 2 Domain Access Control Register Register 3 Undefined Register 4 Fault Status Register Register 5 Fault Address Register Register 6 C...

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