background image

AUTOMOTIVE 80C51FA/83C51FA

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters. The first char-

acter is always a `T' (stands for time). The other

characters, depending on their positions, stand for

the name of a signal or the logical status of that

signal. The following is a list of all the characters and

what they stand for.

A: Address

C: Clock

D: Input Data

H: Logic level HIGH

I: Instruction (program memory contents)

L: Logic level LOW, or ALE

P: PSEN

Q: Output Data

R: RD signal

T: Time

V: Valid

W: WR signal

X: No longer a valid logic level

Z: Float

For example,

T

AVLL

e

Time from Address Valid to ALE Low

T

LLPL

e

Time from ALE Low to PSEN Low

AC CHARACTERISTICS

(T

A

e b

40

§

C to

a

125

§

C, V

CC

e

5V

g

10%, V

SS

e

0V, Load Capacitance

for Port 0, ALE/PROG and PSEN

e

100 pF, Load Capacitance for All Other Outputs

e

80 pF)

EXTERNAL MEMORY CHARACTERISTICS

Symbol

Parameter

12 MHz Oscillator

Variable Oscillator

Units

Min

Max

Min

Max

1/T

CLCL

Oscillator Frequency

3.5

16

MHz

T

LHLL

ALE Pulse Width

127

2T

CLCL

b

40

ns

T

AVLL

Address Valid to ALE Low

43

T

CLCL

b

40

ns

T

LLAX

Address Hold After ALE Low

53

T

CLCL

b

30

ns

T

LLIV

ALE Low to Valid Instruction In

224

4T

CLCL

b

110

ns

T

LLPL

ALE Low to PSEN Low

53

T

CLCL

b

30

ns

T

PLPH

PSEN Pulse Width

205

3T

CLCL

b

45

ns

T

PLIV

PSEN Low to Valid Instruction In

135

3T

CLCL

b

115

ns

T

PXIX

Input Instr Hold After PSEN Trans

0

0

ns

T

PXIZ

Input Instr Float After PSEN Trans

59

T

CLCL

b

25

ns

T

AVIV

Address to Valid Instruction In

302

5T

CLCL

b

115

ns

T

PLAZ

PSEN Low to Address Float

10

10

ns

T

RLRH

RD Pulse Width

400

6T

CLCL

b

100

ns

T

WLWH

WR Pulse Width

400

6T

CLCL

b

100

ns

T

RLDV

RD Low to Valid Data In

242

5T

CLCL

b

175

ns

T

RHDX

Data Hold After RD High

b

10

b

10

ns

T

RHDZ

Data Float After RD High

107

2T

CLCL

b

60

ns

T

LLDV

ALE Low to Valid Data In

507

8T

CLCL

b

160

ns

T

AVDV

Address Valid to Valid Data In

575

9T

CLCL

b

175

ns

T

LLWL

ALE Low to RD or WR Low

200

300

3T

CLCL

b

50

3T

CLCL

a

50

ns

T

AVWL

Data Valid to WR Low

203

4T

CLCL

b

130

ns

T

QVWX

Address Valid before WR Low

23

T

CLCL

b

50

ns

T

WHQX

Data Hold after WR High

33

T

CLCL

b

50

ns

T

QVWH

Data Valid to WE High

433

7T

CLCL

b

150

ns

T

RLAZ

RD Low to Address Float

0

0

ns

T

WHLH

RD or WR High to ALE High

43

123

T

CLCL

b

40

T

CLCL

a

40

ns

10

Summary of Contents for 80C51FA

Page 1: ...Power Down Modes Y ONCE On Circuit Emulation Mode Y Available in PLCC and PDIP Packages See Packaging Specification Order 231369 Y Available in 12 MHz and 16 MHz Versions MEMORY ORGANIZATION PROGRAM M...

Page 2: ...AUTOMOTIVE 80C51FA 83C51FA 270501 1 Figure 1 83C51FA Block Diagram 2...

Page 3: ...are guaranteed over the temperature range of 40 C to 85 C ambient For the automo tive temperature range option operational charac teristics are guaranteed over the temperature range of 40 C to 125 C...

Page 4: ...l features of the 83C51FA Port Pin Alternate Function P1 0 T2 External Count Input to Timer Counter 2 P1 1 T2EX Timer Counter 2 Capture Reload Trigger and Direction Control P1 2 ECI External Count Inp...

Page 5: ...ead strobe to external Program Memory When the 83C51FA is executing code from external Program Memory PSEN is activated twice each ma chine cycle except that two PSEN activations are skipped during ea...

Page 6: ...is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down DESIGN CONSIDERATION When the Idle mode is terminated by a har...

Page 7: ...is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability DC CHARACTERISTICS TA e b40 C to a125 C VCC e 5V g10 VSS e 0V Symbol Parameter Min Typ Max Unit...

Page 8: ...pFs the noise pulse on the ALE signal may exceed 0 8V In these cases it may be desirable to qualify ALE with a Schmitt Trigger or use an Address Latch with a Schmitt Trigger Strobe input 2 Capacitive...

Page 9: ...s Frequency 270501 8 TCLCH e TCHCL e 5 ns Figure 7 ICC Test Condition Active Mode All other pins disconnected 270501 9 TCLCH e TCHCL e 5 ns Figure 8 ICC Test Condition Idle Mode All other pins disconn...

Page 10: ...h 127 2TCLCLb40 ns TAVLL Address Valid to ALE Low 43 TCLCLb40 ns TLLAX Address Hold After ALE Low 53 TCLCLb30 ns TLLIV ALE Low to Valid Instruction In 224 4TCLCLb110 ns TLLPL ALE Low to PSEN Low 53 TC...

Page 11: ...AUTOMOTIVE 80C51FA 83C51FA EXTERNAL PROGRAM MEMORY READ CYCLE 270501 12 EXTERNAL DATA MEMORY READ CYCLE 270501 13 EXTERNAL DATA MEMORY WRITE CYCLE 270501 14 11...

Page 12: ...etup to Clock 700 10TCLCLb133 ns Rising Edge TXHQX Output Data Hold after 50 2TCLCLb117 ns Clock Rising Edge TXHDX Input Data Hold After Clock 0 0 ns Rising Edge TXHDV Clock Rising Edge to Input 700 1...

Page 13: ...RST pin is now RESET pin 3 RST pin description is now RESET pin description 4 Figure 6 ICC vs Frequency has been corrected to show test conditions 5 ICC Max spec has been corrected 6 A C Characterist...

Reviews: