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8XC196KC/8XC196KC20

PROCESS INFORMATION

This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliabili-
ty information is available in Intel’s

Components

Quality and Reliability Handbook,

Order Number

210997.

270942 – 43

EXAMPLE:

N87C196KC is 68-Lead PLCC OTPROM,

16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).

NOTE:

1. EPROMs are available as One Time Programmable
(OTPROM) only.

Figure 3. The 8XC196KC Family Nomenclature

Table 1. Thermal Characteristics

Package

i

ja

i

jc

Type

PLCC

35

§

C/W

13

§

C/W

QFP

55

§

C/W

16

§

C/W

SQFP

TBD

TBD

All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel

Packaging Handbook (order number 240800) for a

description of Intel’s thermal impedance test methodology.

Table 2. 8XC196KC Memory Map

Description

Address

External Memory or I/O

0FFFFH

06000H

Internal ROM/OTPROM or External

5FFFH

Memory (Determined by EA)

2080H

Reserved. Must contain FFH.

207FH

(Note 5)

205EH

PTS Vectors

205DH

2040H

Upper Interrupt Vectors

203FH

2030H

ROM/OTPROM Security Key

202FH

2020H

Reserved. Must contain FFH.

201FH

(Note 5)

201AH

Reserved. Must Contain 20H

2019H

(Note 5)

CCB

2018H

Reserved. Must contain FFH.

2017H

(Note 5)

2014H

Lower Interrupt Vectors

2013H
2000H

Port 3 and Port 4

1FFFH

1FFEH

External Memory

1FFDH

0200H

488 Bytes Register RAM (Note 1)

01FFH

0018H

CPU SFR’s (Notes 1, 3, 4)

0017H
0000H

NOTES:

1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5.

WARNING:

Reserved memory locations must not be

written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.

3

Summary of Contents for 80c196kc

Page 1: ...Y 3 Pulse Width Modulated Outputs Y Four 16 Bit Software Timers Y 8 or 10 Bit A D Converter with Sample Hold Y HOLD HLDA Bus Protocol Y OTPROM One Time Programmable Version The 80C196KC 16 bit microc...

Page 2: ...8XC196KC 8XC196KC20 270942 1 Figure 1 8XC196KC Block Diagram IOC3 0CH HWIN1 READ WRITE 270942 45 NOTE RSV Reserved bits must be e 0 Figure 2 8XC196KC New SFR Bit CLKOUT Disable 2...

Page 3: ...Table 2 8XC196KC Memory Map Description Address External Memory or I O 0FFFFH 06000H Internal ROM OTPROM or External 5FFFH Memory Determined by EA 2080H Reserved Must contain FFH 207FH Note 5 205EH PT...

Page 4: ...8XC196KC 8XC196KC20 270942 2 Figure 4 68 Lead PLCC Package 4...

Page 5: ...8XC196KC 8XC196KC20 270942 40 Figure 5 S8XC196KC 80 Pin QFP Package 5...

Page 6: ...8XC196KC 8XC196KC20 270942 44 Figure 6 80 Pin SQFP Package 6...

Page 7: ...directed to off chip memory Also used to enter programming mode ALE ADV Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a signal to demultiplex the address fr...

Page 8: ...e CPVER Cummulative Program Output Verification Pin is high if all locations have programmed correctly since entering a programming mode PALE A falling edge in Slave Programming Mode and Auto Configur...

Page 9: ...ING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias Commercial Temp 0 a70 C TA Ambient Temperature Under Bias Extended Temp b40 a85 C VCC Digital Supply Voltage 4 50 5 50...

Page 10: ...21 30 mA XTAL1 e 20 MHz VCC e VPP e VREF e 5 5V IPD Powerdown Mode Current 8 15 mA VCC e VPP e VREF e 5 5V IREF A D Converter Reference Current 2 5 mA VCC e VPP e VREF e 5 5V RRST Reset Pullup Resisto...

Page 11: ...Description Min Max Units Notes TAVYV Address Valid to READY Setup 2 TOSC b 68 ns TYLYH Non READY Time No upper limit ns TCLYX READY Hold after CLKOUT Low 0 TOSC b 30 ns Note 1 TLLYX READY Hold after...

Page 12: ...b 35 ns TLLRL ALE Falling Edge to RD Falling Edge TOSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge a4 a30 ns TRLRH RD Low Period TOSC b 5 ns Note 4 TRHLH RD Rising Edge to ALE Rising Edge TOSC TOSC a...

Page 13: ...8XC196KC 8XC196KC20 System Bus Timings 270942 18 13...

Page 14: ...8XC196KC 8XC196KC20 READY Timings One Wait State 270942 20 Buswidth Timings 270942 35 14...

Page 15: ...kly Driven a20 ns TCLHAH CLKOUT Low to HLDA High b15 a15 ns TCLBRH CLKOUT Low to BREQ High b15 a15 ns THAHAX HLDA High to Address No Longer Float b15 ns THAHBV HLDA High to BHE INST RD WR Valid b10 a1...

Page 16: ...Bit External Execution 2 5 States 8 Bit External Execution 4 5 States EXTERNAL CLOCK DRIVE 8XC196KC Symbol Parameter Min Max Units 1 TXLXL Oscillator Frequency 8 16 0 MHz TXLXL Oscillator Period 62 5...

Page 17: ...sing crystals C1 e C2 20 pF When using ceramic resonators consult manufacturer for recommended cir cuitry EXTERNAL CLOCK CONNECTIONS 270942 42 NOTE Required if TTL driver used Not needed if CMOS drive...

Page 18: ...r Min Max Units TXLXL Serial Port Clock Period BRR t 8002H 6 TOSC ns TXLXH Serial Port Clock Falling Edge 4 TOSC b50 4 TOSC a50 ns to Rising Edge BRR t 8002H TXLXL Serial Port Clock Period BRR e 8001H...

Page 19: ...fset Error 0 25 g 0 5 LSBs Non Linearity 1 0 g 2 0 0 g3 LSBs Differential Non Linearity Error lb1 a2 LSBs Channel to Channel Matching g0 1 0 g1 LSBs Repeatability g0 25 LSBs Temperature Coefficients O...

Page 20: ...Non Linearity Error lb1 a1 LSBs Channel to Channel Matching g1 LSBs Repeatability g0 25 LSBs Temperature Coefficients Offset 0 003 LSB C Full Scale 0 003 LSB C Differential Non Linearity 0 003 LSB C O...

Page 21: ...ANGND should nominally be at the same potential 0V 4 Load capacitance during Auto and Slave Mode programming e 150 pF AC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Units TSHLL Reset...

Page 22: ...apply VPP until VCC is stable and within specifications and the oscillator clock has stabilized or the device may be damaged EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH...

Page 23: ...ime Programming use the section of code in the 8XC196KC User s Guide 4 ONCE Mode Entry The ONCE mode is entered on the 8XC196KC by driving the TXD pin low on the rising edge of RESET The TXD pin is he...

Page 24: ...as changed to 55 C W from 42 C W 6 iJC for QFP package was changed to 16 C W from TBD C W 7 TSAM MIN in 10 bit mode was changed to 1 0 ms from 3 0 ms 8 TSAM MIN in 8 bit mode was changed to 1 0 ms fro...

Page 25: ...ations and bitmaps 3 Added programming pin function to package drawings and pin descriptions 4 Changed absolute maximum temperature under bias from 0 C to a70 C to b55 C to a125 C 5 Replaced VOH2 spec...

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