Intel 80c196kc, Manual

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8XC196KC/8XC196KC20
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
270942 – 29
8XC196KB TO 8XC196KC DESIGN
CONSIDERATIONS
1. Memory Map. The 8XC196KC has 512 bytes of
RAM/SFRs and an optional 16K of
ROM/OTPROM. The extra 256 bytes of RAM will
reside in locations 100H – 1FFH and the extra 8K
of
ROM/OTPROM will reside in locations
4000H – 5FFFH. These locations are external
memory on the 8XC196KB.
2. The CDE pin on the KB has become a V
SS
pin on
the KC to support 16/20 MHz operation.
3. EPROM programming. The 8XC196KC has a dif-
ferent programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code in the
8XC196KC User’s Guide.
4. ONCE Mode Entry. The ONCE mode is entered
on the 8XC196KC by driving the TXD pin low on
the rising edge of RESET. The TXD pin is held
high by a pullup that is specified by I
OH1
. This
Pullup must not be overridden or the 8XC196KC
will enter the ONCE mode.
5. During the bus HOLD state, the 8XC196KC
weakly holds RD, WR, ALE, BHE and INST in
their inactive states. The 8XC196KB only holds
ALE in its inactive state.
6. A RESET pulse from the 8XC196KC is 16 states
rather than 4 states as on the 8XC196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
8XC196KC ERRATA
1. Missed EXTINT on P0.7.
The 80C196KC20 could possibly miss an
EXTINT on P0.7. See techbit MC0893.
2. HSIÐMODE divide-by-eight.
See Faxback
Ý 2192.
3. IPD hump.
See Faxback Ý 2311.
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