80C196KB USER’S GUIDE
270651 – 25
Figure 9-4. I/O Status Register 0
Writing the time value loads the HSO Holding Register
with both the time and the last written command tag.
The command does not actually enter the CAM file
until an empty CAM register becomes available.
Commands in the holding register will not execute even
if their time tag is reached. Commands must be in the
CAM to execute. Commands in the holding register
can also be overwritten. Since it can take up to 8 state
times for a command to move from the holding register
to the CAM, 8 states must be allowed between succes-
sive writes to the CAM.
To provide proper synchronization, the minimum time
that should be loaded to Timer1 is Timer1
a
2. Small-
er values may cause the Timer match to occur 65,636
counts later than expected. A similar restriction applies
if Timer2 is used.
Care must be taken when writing the command tag for
the HSO, because an interrupt can occur between writ-
ing the command tag and loading the time value. If the
interrupt service routine writes to the HSO, the com-
mand tag used in the interrupt routine will overwrite
the command tag from the main routine. One way of
avoiding this problem would be to disable interrupts
when writing to the HSO unit.
9.3 HSO Status
Before writing to the HSO, it is desirable to ensure that
the Holding Register is empty. If it is not, writing to the
HSO will overwrite the value in the Holding Register.
I/O Status Register 0 (IOS0) bits 6 and 7 indicate the
status of the HSO unit. If IOS0.6 equals 0, the holding
register is empty and at least one CAM register is emp-
ty. If IOS0.7 equals 0, the holding register is empty.
The programmer should carefully decide which of these
two flags is the best to use for each application. This
register also shows the current status of the HSO.0
through HSO.5. The HSO pins can be set by writing to
270651 – 26
Figure 9-5. I/O Status Register 1 (IOS1)
this register in Window 15. The format for I/O Status
Register 0 is shown in Figure 9-4.
The expiration of software timer 0 through 4, and the
overflow of Timer1 and Timer2 are indicated in IOS1.
The status bits can be set in Window 15 but not cause
interrupts. The register is shown in Figure 9-5.
Whenever the processor reads this register all of the
time-related flags (bits 5 through 0) are cleared. This
applies not only to explicit reads such as:
LDB
AL,IOS1
but also to implicit reads such as:
JBS
IOS1,3,somewhere else
which jumps to somewhereÐelse if bit 3 of IOS1 is set.
In most cases this situation can best be handled by hav-
ing a byte in the register file which maintains an image
of the register. Any time a hardware timer interrupt or
a HSO software timer interrupt occurs the byte can be
updated:
ORB
IOS1 image,IOS1
leaving IOS1Ðimage containing all the flags that were
set before plus all the new flags that were read and
cleared from IOS1. Any other routine which needs to
sample the flags can safely check IOS1Ðimage. Note
that if these routines need to clear the flags that they
have acted on, then the modification of IOS1Ðimage
must be done from inside a critical region.
9.4 Clearing the HSO and Locked
Entries
All 8 CAM locations of the HSO are compared before
any action is taken. This allows a pending external
43
数控原理与维修
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Summary of Contents for 80C196KB Series
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