80C196KB USER’S GUIDE
4.1 Pulse Width Modulation Output
(D/A)
Digital to analog conversion can be done with the Pulse
Width Modulation output. The output waveform is a
variable duty cycle pulse which repeats every 256 state
times or 512 state times if the prescaler is enabled.
Changes in the duty cycle are made by writing to the
PWM register. There are several types of motors which
require a PWM waveform for most efficient operation.
Additionally, if this waveform is integrated it will pro-
duce a DC level which can be changed in 256 steps by
varying the duty cycle. Details on the PWM are in Sec-
tion 6.
4.2 Timers
Two 16-bit timers are available for use on the
80C196KB. The first is designated ‘‘Timer1’’, the sec-
ond ‘‘Timer2’’. Timer1 is used to synchronize events to
real time, while Timer2 is clocked externally and syn-
chronizes events to external occurrences. The timers
are the time bases for the High Speed Input (HSI) and
High Speed Output (HSO) units and can be considered
an integral part of the HSI/O. Details on the timers are
in Section 7.
Timer1 is a free-running timer which is incremented
every eight state times, just as it is on the 8096BH.
Timer1 can cause an interrupt when it overflows.
Timer2 counts transitions, both positive and negative,
on its input which can be either the T2CLK pin or the
HSI.1 pin. Timer2 can be read and written and can be
reset by hardware, software or the HSO unit. It can be
used as an up/down counter based on Port 2.6 and it’s
value can be captured into the T2CAPture register. In-
terrupts can be generated on capture events and if Tim-
er2 crosses the 0FFFFH/0000H boundary or the
7FFFH/8000H boundary in either direction.
4.3 High Speed Inputs (HSI)
The High Speed Input (HSI) unit can capture the value
of Timer1 when an event takes place on one of four
input pins (HSI.0-HSI.3). Four types of events can trig-
ger a capture: rising edges only, falling edges only, ris-
ing or falling edges, or every eighth rising edge. A block
diagram of this unit is shown in Figure 4-3. Details on
the HSI unit are in Section 8.
When events occur, the Timer1 value gets stored in the
FIFO along with 4 status bits which indicate the input
line(s) that caused the event. The next event ready to be
unloaded from the FIFO is placed in the HSI Holding
Register, so a total of 8 pieces of data can be stored in
the FIFO. Data is taken off the FIFO by reading the
HSIÐSTATUS register, followed by reading the
HSIÐTIME register. When the time register is read
the next FIFO location is loaded into the holding regis-
ter.
Three forms of HSI interrupts can be generated: when a
value moves from the FIFO into the holding register;
when the FIFO (independent of the holding register)
has 4 or more events stored; and when the FIFO has 6
or more events stored. This flexibility allows optimiza-
tion of the HSI for the expected frequency of interrupts.
Independent of the HSI operation, the state of the HSI
pins is indicated by 4 bits of the HSIÐSTATUS regis-
ter. Also independent of the HSI operation is the HSI.0
pin interrupt, which can be used as an extra external
interrupt even if the pin is not enabled to the HSI unit.
4.4 High Speed Outputs (HSO)
The High Speed Output (HSO) unit can generate events
at specified times or counts based on Timer1 or Timer2
with minimal CPU overhead. A block diagram of the
HSO unit is shown in Figure 4-4. Up to 8 pending
events can be stored in the CAM (Content Addressable
Memory) of the HSO unit at one time. Commands are
placed into the HSO unit by first writing to HSOÐ
COMMAND with the event to occur, and then to
HSOÐTIME with the timer match value.
Fourteen different types of events can be triggered by
the HSO: 8 external and 6 internal. There are two inter-
rupt vectors associated with the HSO, one for external
events, and one for internal events. External events con-
sist of switching one or more of the 6 HSO pins
(HSO.0-HSO.5). Internal events include setting up 4
Software Timers, resetting Timer2, and starting an A/
D conversion. The software timers are flags that can be
set by the HSO and optionally cause interrupts. Details
on the HSO Unit are in Section 9.
4.5 Serial Port
The serial port on the 80C196KB is functionally com-
patible with the serial port on the MCS-51 and MCS-96
families of microcontrollers. One synchronous and
three asynchronous modes are available. The asynchro-
nous modes are full duplex, meaning they can transmit
and receive at the same time. Double buffering is pro-
vided for the receiver so that a second byte can be re-
ceived before the first byte has been read. The transmit-
ter is also double buffered, allowing bytes to be written
while transmission is still in progress.
The Serial Port STATus (SPÐSTAT) register contains
bits to indicate receive overrun, parity, and framing er-
rors, and transmit and receive interrupts. Details on the
Serial Port are in Section 10.
24
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Summary of Contents for 80C196KB Series
Page 1: ...November 1990 80C196KB User s Guide Order Number 270651 003 http www agreenleaf cn...
Page 59: ...80C196KB USER S GUIDE Figure 11 7 Ideal A D Characteristic 270651 37 55 http www agreenleaf cn...
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