80C186EB/80C188EB, 80L186EB/80L188EB
INTRODUCTION
Unless specifically noted, all references to the
80C186EB apply to the 80C188EB, 80L186EB, and
80L188EB. References to pins that differ between
the 80C186EB/80L186EB and the 80C188EB/
80L188EB are given in parentheses. The ‘‘L’’ in the
part number denotes low voltage operation. Physi-
cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are
identical.
The 80C186EB is the first product in a new genera-
tion of low-power, high-integration microprocessors.
It enhances the existing 186 family by offering new
features and new operating modes. The 80C186EB
is object code compatible with the 80C186XL/
80C188XL microprocessors.
The 80L186EB is the 3V version of the 80C186EB.
The 80L186EB is functionally identical to the
80C186EB
embedded
processor.
Current
80C186EB users can easily upgrade their designs to
use the 80L186EB and benefit from the reduced
power consumption inherent in 3V operation.
The feature set of the 80C186EB meets the needs
of low power, space critical applications. Low-Power
applications benefit from the static design of the
CPU core and the integrated peripherals as well as
low voltage operation. Minimum current consump-
tion is achieved by providing a Powerdown mode
that halts operation of the device, and freezes the
clock circuits. Peripheral design enhancements en-
sure that non-initialized peripherals consume little
current.
Space critical applications benefit from the inte-
gration of commonly used system peripherals. Two
serial channels are provided for services such as
diagnostics, inter-processor communication, modem
interface, terminal display interface, and many oth-
ers. A flexible chip select unit simplifies memory and
peripheral interfacing. The interrupt unit provides
sources for up to 129 external interrupts and will pri-
oritize these interrupts with those generated from
the on-chip peripherals. Three general purpose tim-
er/counters and sixteen multiplexed I/O port pins
round out the feature set of the 80C186EB.
Figure 1 shows a block diagram of the 80C186EB/
80C188EB. The Execution Unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhance
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions,
string move instructions that operate at full bus
bandwidth, ten new instruction, and fully static oper-
ation. The Bus Interface Unit (BIU) is the same as
that found on the original 186 family products, ex-
cept the queue status mode has been deleted and
buffer interface control has been changed to ease
system design timings. An independent internal bus
is used to allow communication between the BIU
and internal peripherals.
CORE ARCHITECTURE
Bus Interface Unit
The 80C186EB core incorporates a bus controller
that generates local bus control signals. In addition,
it employs a HOLD/HLDA protocol to share the local
bus with other bus masters.
The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information, and data (for write operations) in-
formation. It is also responsible for reading data off
the local bus during a read operation. A READY in-
put pin is provided to extend a bus cycle beyond the
minimum four states (clocks).
The local bus controller also generates two control
signals (DEN and DT/R) when interfacing to exter-
nal transceiver chips. (Both DEN and DT/R are
available on the PLCC devices, only DEN is avail-
able on the QFP and SQFP devices.) This capability
allows the addition of transceivers for simple buffer-
ing of the multiplexed address/data bus.
Clock Generator
The processor provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide-
by-two counter, and two low-power operating
modes.
The oscillator circuit is designed to be used with ei-
ther a
parallel resonant
fundamental or third-over-
tone mode crystal network. Alternatively, the oscilla-
tor circuit may be driven from an external clock
source. Figure 2 shows the various operating modes
of the oscillator circuit.
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter. This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components. All AC timings are referenced to
CLKOUT.
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