80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions
(Continued)
Pin
Pin
Input
Output
Description
Name
Type
Type
States
DT/R
O
Ð
H(Z)
Data Transmit/Receive
output controls the direction of a
bi-directional buffer in a buffered system. DT/R is only
R(Z)
available for the PLCC package.
P(X)
LOCK
O
Ð
H(Z)
LOCK
output indicates that the bus cycle in progress is not
to be interrupted. The processor will not service other bus
R(WH)
requests (such as HOLD) while LOCK is active. This pin is
P(1)
configured as a weakly held high input while RESIN is
active and must not be driven low.
HOLD
I
A(L)
Ð
HOLD
request input to signal that an external bus master
wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix.
HLDA
O
Ð
H(1)
HoLD Acknowledge
output to indicate that the processor
has relinquished control of the local bus. When HLDA is
R(0)
asserted, the processor will (or has) floated its data bus
P(0)
and control signals allowing another bus master to drive the
signals directly.
NCS
O
Ð
H(1)
Numerics Coprocessor Select
output is generated when
accessing a numerics coprocessor. NCS is not provided on
(N.C.)
R(1)
the QFP or SQFP packages. This signal does not exist on
P(1)
the 80C188EB/80L188EB.
ERROR
I
A(L)
Ð
ERROR
input that indicates the last numerics coprocessor
operation resulted in an exception condition. An interrupt
(N.C.)
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation. ERROR is not provided
on the QFP or SQFP packages. This signal does not exist
on the 80C188EB/80L188EB.
PEREQ
I
A(L)
Ð
CoProcessor REQuest
signals that a data transfer
between an External Numerics Coprocessor and Memory is
(N.C.)
pending. PEREQ is not provided on the QFP or SQFP
packages. This signal does not exist on the 80C188EB/
80L188EB.
UCS
O
Ð
H(1)
Upper Chip Select
will go active whenever the address of
a memory or I/O bus cycle is within the address limitations
R(1)
programmed by the user. After reset, UCS is configured to
P(1)
be active for memory accesses between 0FFC00H and
0FFFFFH.
LCS
O
Ð
H(1)
Lower Chip Select
will go active whenever the address of
a memory bus cycle is within the address limitations
R(1)
programmed by the user. LCS is inactive after a reset.
P(1)
P1.0/GCS0
O
Ð
H(X)/H(1)
These pins provide a multiplexed function. If enabled, each
pin can provide a
Generic Chip Select
output which will go
P1.1/GCS1
R(1)
active whenever the address of a memory or I/O bus cycle
P1.2/GCS2
P(X)/P(1)
is within the address limitations programmed by the user.
P1.3/GCS3
When not programmed as a Chip-Select, each pin may be
P1.4/GCS4
used as a general purpose output
Port.
As an output port
P1.5/GCS5
pin, the value of the pin can be read internally.
P1.6/GCS6
P1.7/GCS7
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
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