Intel 80960KB Manual Download

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80960KB

5.0

REVISION HISTORY

No revision history was maintained in earlier revisions of this data sheet. All errata that has been

identified to date is incorporated into this revision. The sections significantly changed since the

previous revision are:

Section

Last

Rev.

Description

Table 4. 80960KB Pin

Description: L-Bus Signals (pg. 8)

-005

LOCK pin description rewritten for clarity.

2.3. Connection Recommenda-

tions (pg. 11)

-005

Changed suggested open-drain termination networks to reflect

more realistic operating conditions with reduction in DC power

consumption.

Figure 9. Typical Current vs.

Frequency (Hot Temp) (pg. 13)

-005

Added figure for typical power supply current at hot

temperature to aid thermal analysis.

Figure 12. Test Load Circuit for

Three-State Output Pins (pg. 14)
Figure 13. Test Load Circuit for

Open-Drain Output Pins (pg. 14)

-005

All outputs now specified with standard 50 pF test loads to

agree with actual test methodology.

2.7. DC Characteristics (pg. 15)

-005

ICC max specification reduced:

WAS:

IS:

AT:

375 mA

315 mA

16 MHz

420 mA

360 mA

20 MHz

480 mA

420 mA

25 MHz

Figures 7, 8, 9, 23, 24, 25 and 26 have also been changed

accordingly.

2.8. AC Specifications (pg. 16)

-005

25 MHz operation extended to product in PQFP package. T

min. improved at all frequencies from 0 ns to 2 ns and T

max.

improved from 20 ns to 18 ns.
T

max improvement:

WAS:

IS:

AT:

31ns

28ns

16 MHz

26ns

23ns

20 MHz

24ns

23ns

25 MHz

Functional Waveforms

-005

Redrawn for clarity. CLK signal drawn with more likely phase

relationship to CLK2. Open-drain output signals drawn to show

correct inactive states.

Various

-005

Deleted all references to 10 MHz. Intel no longer offers a

10 MHz 80960KB device.

Table 4. 80960KB Pin

Description: L-Bus Signals (pg. 8)

-006

DEN pin description omitted from revision -005.

Figure 18, 80960KB PGA

Pinout—View from Bottom (Pins

Facing Up) (pg. 22)

-006

Pin M2 was N.C., now shows as V

Pin M13 was V

, now shows as N.C.

Revision -008

To address the fact that many of the package prefix variables have changed, all package

prefix variables in this document are now indicated with an "x".

Summary of Contents for 80960KB

Page 1: ...boarding 4 Gigabyte Linear Address Space Pin Compatible with 80960KA Built in Interrupt Controller 31 Priority Levels 256 Vectors 3 4 µs Latency 25 MHz Easy to Use High Bandwidth 32 Bit Bus 66 7 Mbytes s Burst Up to 16 Bytes Transferred per Burst 132 Lead Packages Pin Grid Array PGA Plastic Quad Flat Pack PQFP On Chip Floating Point Unit Supports IEEE 754 Floating Point Standard Four 80 Bit Regist...

Page 2: ...ed for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel retains the right to make changes to specifications and product descriptions at any time without notice...

Page 3: ...g 6 1 1 9 Debug Features 6 1 1 10 Fault Detection 7 1 1 11 Built in Testability 7 2 0 ELECTRICAL SPECIFICATIONS 10 2 1 Power and Grounding 10 2 2 Power Decoupling Recommendations 10 2 3 Connection Recommendations 11 2 4 Characteristic Curves 11 2 5 Test Load Circuit 14 2 7 DC Characteristics 15 2 6 Absolute Maximum Ratings 15 2 8 AC Specifications 16 2 8 1 AC Specification Tables 17 3 0 MECHANICAL...

Page 4: ...essor Clock Pulse CLK2 20 Figure 15 RESET Signal Timing 20 Figure 16 132 Lead Pin Grid Array PGA Package 21 Figure 17 80960KA PGA Pinout View from Bottom Pins Facing Up 22 Figure 18 80960KA PGA Pinout View from Top Pins Facing Down 23 Figure 19 80960KA 132 Lead Plastic Quad Flat Pack PQFP Package 23 Figure 20 PQFP Pinout View From Top 24 Figure 21 HOLD Timing 30 Figure 22 16 MHz Maximum Allowable ...

Page 5: ...acteristics 15 Table 6 80960KA AC Characteristics 16 MHz 17 Table 7 80960KA AC Characteristics 20 MHz 18 Table 9 80960KA PGA Pinout In Pin Order 25 Table 10 80960KA PGA Pinout In Signal Order 26 Table 11 80960KA PQFP Pinout In Pin Order 27 Table 12 80960KA PQFP Pinout In Signal Order 28 Table 13 80960KA PGA Package Thermal Characteristics 29 Table 14 80960KA PQFP Package Thermal Characteristics 30...

Page 6: ......

Page 7: ...ormance Since time to market is critical embedded microprocessors need to be easy to use in both hardware and software designs All members of the i960 processor family share a common core architecture which utilizes RISC technology so that except for special functions the family members are object code compatible Each new processor in the family adds its own special set of functions to the core to...

Page 8: ...it possible to eliminate the instruction alignment stage in the pipeline To simplify the instruction decoder there are only five instruction formats each instruction uses only one format See Figure 3 5 Overlapped Instruction Execution Load operations allow execution of subsequent instructions to continue before the data has been returned from memory so that these instructions can overlap the load ...

Page 9: ...l Branch Compare and Branch Call Call Extended Call System Return Branch and Link Conditional Fault Synchronize Faults Debug Miscellaneous Decimal Floating Point Modify Trace Controls Mark Force Mark Atomic Add Atomic Modify Flush Local Registers Modify Arithmetic Controls Scan Byte for Equal Test Condition Code Modify Process Controls Decimal Move Decimal Add with Carry Decimal Subtract with Carr...

Page 10: ...meric 8 16 32 and 64 bit ordinals 8 16 32 and 64 bit integers 32 64 and 80 bit real numbers Non Numeric Bit Bit Field Triple Word 96 bits Quad Word 128 bits 1 1 3 Large Register Set The 80960KB programming environment includes a large number of registers In fact 32 registers are available at any time The availability of this many registers greatly reduces the number of memory accesses required to ...

Page 11: ...ted in a steady stream but consist of many branches loops and procedure calls that lead to jumping back and forth in the same small section of code Thus by maintaining a block of instructions in cache the number of memory references required to read instructions into the processor is greatly reduced To load the instruction cache instructions are fetched in 16 byte blocks up to four instructions ca...

Page 12: ...for both mandatory and recommended portions of IEEE Standard 754 for floating point arithmetic including all arithmetic exponential logarithmic and other transcendental functions Table 3 shows execution times for some representative instructions 1 1 8 High Bandwidth Local Bus The 80960KB CPU resides on a high bandwidth address data bus known as the local bus L Bus The L Bus provides a direct commu...

Page 13: ...80960KB s tracing mechanisms implemented completely in hardware greatly simplify the task of software test and debug 1 1 11 Fault Detection The 80960KB has an automatic mechanism to handle faults Fault types include floating point trace and arithmetic faults When the processor detects a fault it automatically calls the appropriate fault handling routine and saves the current instruction pointer an...

Page 14: ...remains valid during Td cycles DT R O O D DATA TRANSMIT RECEIVE indicates the direction of data transfer to and from the L Bus It is low during Ta and Td cycles for a read or interrupt acknowl edgment it is high during Ta and Td cycles for a write DT R never changes state when DEN is asserted DEN O O D DATA ENABLE active low enables data transceivers The processor asserts DEN during all Td and Tw ...

Page 15: ...bus CACHE O T S CACHE indicates when an access is cacheable during a Ta cycle It is not asserted during any synchronous access such as a synchronous load or move instruction used for sending an IAC message The CACHE signal floats to a high impedance state when the processor is idle Table 5 80960KB Pin Description Support Signals Sheet 1 of 2 NAME TYPE DESCRIPTION BADAC I BAD ACCESS if asserted in ...

Page 16: ...is used to receive an interrupt request from an external interrupt controller INT3 INTA I O O D INTERRUPT3 INTERRUPT ACKNOWLEDGE The bus interrupt control register determines how this pin is interpreted If INT3 it has the same interpretation as the INT0 INT1 and INT2 pins If INTA it is used as an output to control interrupt acknowledge transactions The INTA output is latched on chip and remains va...

Page 17: ...dance of 100 Ω Terminating output signals in this fashion limits signal swing and reduces AC power consumption NOTE Do not connect external logic to pins marked N C Figure 5 Connection Recommendations for Low Current Drive Network Figure 6 Connection Recommendations for High Current Drive Network 2 4 Characteristic Curves Figure 7 shows typical supply current requirements over the operating temper...

Page 18: ...Frequency Room Temp 60 40 20020406080100120140 VCC 5 0 V POWER SUPPLY CURRENT mA CASE TEMPERATURE C 25 MHz 20 MHz 16 MHz 380 360 340 320 300 280 260 240 220 200 OPERATING FREQUENCY MHz 4 5V 5 0V 5 5V TYPICAL SUPPLY CURRENT mA TEMP 22 C 400 380 360 340 320 300 280 260 240 220 200 180 16 20 25 ...

Page 19: ...ive Derating Curve 2 5 Test Load Circuit Figure 12 illustrates the load circuit used to test the 80960KB s three state pins Figure 13 shows the load circuit used to test the open drain outputs The open drain test uses an active load circuit in the form 0 10 20 30 40 50 0 8 0 6 0 4 0 2 0 0 OUTPUT LOW CURRENT mA TEMP 85 C VCC 4 5V OUTPUT LOW VOLTAGE V 0 20 40 60 80 100 30 25 20 15 10 CAPACITIVE LOAD...

Page 20: ...IOL current source flows through diode D2 When the 80960KB open drain driver under test is on diode D1 is also on and the voltage on the pin being tested drops to VOL Diode D2 turns off and IOL flows through diode D1 Figure 12 Test Load Circuit for Three State Output Pins Figure 13 Test Load Circuit for Open Drain Output Pins THREE STATE OUTPUT CL 50 pF for all signals CL CL OPEN DRAIN OUTPUT IOL ...

Page 21: ...l Parameter Min Max Units Notes VIL Input Low Voltage 0 3 0 8 V VIH Input High Voltage 2 0 VCC 0 3 V VCL CLK2 Input Low Voltage 0 3 0 8 V VCH CLK2 Input High Voltage 0 55 VCC VCC 0 3 V VOL Output Low Voltage 0 45 V 1 2 VOH Output High Voltage 2 4 V 3 4 ICC Power Supply Current 16 MHz 20 MHz 25 MHz 315 360 420 mA mA mA 5 5 5 ILI Input Leakage Current 15 µA 0 VIN VCC ILO Output Leakage Current 15 µA...

Page 22: ...time the TTL levels of LOW 0 8 V or HIGH 2 0 V All AC testing should be done with input voltages of 0 4 V and 2 4 V except for the clock CLK2 which should be tested with input voltages of 0 45 V and 0 55 VCC Figure 14 Drive Levels and Timing Relationships for 80960KB Signals A B C D A B C 1 5V 1 5V 1 5V 1 5V 0 8V T6 1 5V 1 5V T7 1 5V 1 5V VALID OUTPUT T6 T8 T8 T13 T14 1 5V 1 5V VALID OUTPUT T9 2 0...

Page 23: ...lock Low Time CLK2 8 ns VIL 10 Point 1 2V T3 Processor Clock High Time CLK2 8 ns VIH 90 Point 0 1V 0 5 VCC T4 Processor Clock Fall Time CLK2 10 ns VIN 90 Point to 10 Point 1 T5 Processor Clock Rise Time CLK2 10 ns VIN 10 Point to 90 Point 1 Synchronous Outputs T6 Output Valid Delay 2 25 ns T6H HLDA Output Valid Delay 4 28 ns T7 ALE Width 15 ns T8 ALE Output Valid Delay 2 18 ns T9 Output Float Dela...

Page 24: ...LK2 6 ns VIL 10 Point 1 2V T3 Processor Clock High Time CLK2 6 ns VIH 90 Point 0 1V 0 5 VCC T4 Processor Clock Fall Time CLK2 10 ns VIN 90 Point to 10 Point 1 T5 Processor Clock Rise Time CLK2 10 ns VIN 10 Point to 90 Point 1 Synchronous Outputs T6 Output Valid Delay 2 20 ns T6H HLDA Output Valid Delay 4 23 ns T7 ALE Width 12 ns T8 ALE Output Valid Delay 2 18 ns T9 Output Float Delay 2 20 ns 2 T9H...

Page 25: ...e CLK2 5 ns VIL 10 Point 1 2V T3 Processor Clock High Time CLK2 5 ns VIH 90 Point 0 1V 0 5 VCC T4 Processor Clock Fall Time CLK2 10 ns VIN 90 Point to 10 Point 1 T5 Processor Clock Rise Time CLK2 10 ns VIN 10 Point to 90 Point 1 Synchronous Outputs T6 Output Valid Delay 2 18 ns T6H HLDA Output Valid Delay 4 23 ns T7 ALE Width 12 ns T8 ALE Output Valid Delay 2 18 ns T9 Output Float Delay 2 18 ns 2 ...

Page 26: ...EL MIN 0 55VCC LOW LEVEL MAX 0 8V T1 T3 T5 T4 T2 90 10 1 5 V CLK2 CLK RESET OUTPUTS FIRST A B C D A INIT PARAMETERS BADAC INT0 IAC MUST BE SET UP 8 CLOCKS PRIOR TO THIS CLK2 EDGE INIT PARAMETERS MUST BE HELD BEYOND THIS CLK2 EDGE T15 RESET HOLD T16 RESET SETUP T17 RESET WIDTH T15 T16 T17 ...

Page 27: ...ge types are given in the Intel Packaging handbook Order 240800 3 1 1 Pin Assignment The PGA and PQFP have different pin assignments Figure 18 shows the view from the PGA bottom pins facing up and Figure 19 shows a view from the PGA top pins facing down Figure 20 shows the PQFP package Figure 21 shows the PQFP pinout with signal names Notice that the pins are numbered in order from 1 to 132 around...

Page 28: ...DS ALE N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C VSS VCC VSS VCC VSS VSS VSS VSS VCC VCC VCC VCC INT2 INT0 INT1 INT3 LAD3 LAD8 LAD20 LAD13 BADAC HOLD LAD25 RESET LAD0 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD19 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD22 LAD24 LAD23 CLK2 P N M L K J H G F E D C B A P N M L K J H G F E D C B A 14 13 12 11 10 9 8 7 ...

Page 29: ...N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C VSS VCC VSS VCC VSS VSS VSS VSS VCC VCC VCC VCC INT2 INT0 INT1 INT3 LAD3 LAD8 LAD20 LAD13 BADAC HOLD LAD25 RESET LAD0 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD19 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD22 LAD24 LAD23 CLK2 P N M L K J H G F E D C B A P N M L K J H G F E D C B A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11...

Page 30: ...L 1 3 D A L V S S E H C A C R W Y D A E R R T D 0 E B 1 E B 2 E B 3 E B E R U L I A F V S S K C O L N E D V S S V S S C N C N V S S V S S C N V C C V C C C N V S S V S S 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132...

Page 31: ...N C N6 N C A12 LAD1 D3 HLDA J14 N C N7 N C A13 INT2 INTR D12 VCC K1 BE3 N8 N C A14 VCC D13 N C K2 FAILURE N9 N C B1 LAD23 D14 N C K3 VSS N10 N C B2 LAD24 E1 LAD28 K12 VCC N11 N C B3 LAD22 E2 LAD26 K13 N C N12 N C B4 LAD21 E3 LAD27 K14 N C N13 N C B5 LAD18 E12 N C L1 DEN N14 N C B6 LAD15 E13 VSS L2 N C P1 VCC B7 LAD12 E14 N C L3 VCC P2 N C B8 LAD10 F1 LAD29 L12 VSS P3 N C B9 LAD6 F2 LAD31 L13 N C P...

Page 32: ... FAILURE K2 LAD26 E2 N C M13 VCC D12 HLDA D3 LAD27 E3 N C M14 VCC K12 HOLD C1 LAD28 E1 N C N2 VCC L3 IAC INT0 C14 LAD29 F1 N C N3 VCC M2 INT1 C13 LAD30 G1 N C N4 VCC M5 INT2 INTR A13 LAD31 F2 N C N5 VCC M11 INT3 INTA C12 LOCK H3 N C N6 VCC P1 LAD0 B12 N C D13 N C N7 VCC P14 LAD1 A12 N C D14 N C N8 VSS A2 LAD2 B10 N C E12 N C N9 VSS B14 LAD3 C9 N C E14 N C N10 VSS C5 LAD4 A11 N C F12 N C N11 VSS C1...

Page 33: ...AD9 12 READY 45 N C 78 N C 111 LAD10 13 DT R 46 N C 79 VSS 112 LAD11 14 BE0 47 N C 80 VSS 113 LAD12 15 BE1 48 N C 81 N C 114 VSS 16 BE2 49 N C 82 VCC 115 LAD13 17 BE3 50 N C 83 VCC 116 LAD14 18 FAILURE 51 N C 84 VSS 117 LAD15 19 VSS 52 VSS 85 IAC INT0 118 LAD16 20 LOCK 53 VSS 86 INT1 119 LAD17 21 DEN 54 N C 87 NT2 INTR 120 LAD18 22 VSS 55 VCC 88 NT3 INTA 121 LAD19 23 VSS 56 VCC 89 N C 122 LAD20 24...

Page 34: ... 64 VSS 19 FAILURE 18 LAD26 3 N C 65 VSS 22 HLDA 1 LAD27 4 N C 66 VSS 23 HOLD 130 LAD28 5 N C 69 VSS 26 IAC INT0 85 LAD29 6 N C 72 VSS 27 INT1 86 LAD30 7 N C 75 VSS 32 INT2 INTR 87 LAD31 8 N C 76 VSS 33 INT3 INTA 88 LOCK 20 N C 77 VSS 42 LAD0 100 N C 24 N C 78 VSS 52 LAD1 101 N C 25 N C 81 VSS 53 LAD2 102 N C 28 N C 89 VSS 57 LAD3 104 N C 31 N C 94 VSS 67 LAD4 105 N C 34 N C 95 VSS 68 LAD5 106 N C...

Page 35: ...a harsh environment where the ambient temperature may exceed the limits for the normal commercial part consider using an extended temperature device These components are available at 16 20 and 25 MHz in the ceramic PGA package Extended operating temperature range is 40 C to 125 C case Figure 26 shows the maximum allowable ambient temperature for the 20 MHz extended temperature TA80960KB at various...

Page 36: ...w ft min m sec 0 0 50 0 25 100 0 50 200 1 01 400 2 03 600 3 04 800 4 06 θ Junction to Case 9 9 9 9 9 9 9 θ Case to Ambient No Heatsink 22 19 18 16 11 9 8 NOTES 1 This table applies to 80960KB PQFP soldered directly to board 2 θJA θJC θCA 3 θJL 18 C W approx θJB 18 C W approx θJC θJL θJB Th Th Th CLK2 CLK HOLD HLDA T12 T11 T6H T9H ...

Page 37: ... 70 65 60 55 0 200 400 600 800 PQFP PGA with no heatsink PGA with omni directional heatsink PGA with uni directional heatsink AIRFLOW ft min TEMPERATURE o C 90 90 85 80 75 70 65 60 0 200 400 600 800 PQFP PGA with no heatsink PGA with omni directional heatsink PGA with uni directional heatsink AIRFLOW ft min TEMPERATURE o C 55 50 ...

Page 38: ...kage AIRFLOW ft min TEMPERATURE o C 80 75 70 65 60 55 50 45 40 0 100 200 300 400 500 600 700 800 PQFP PGA with no heatsink PGA with omni directional heatsink PGA with uni directional heatsink 85 PGA with no heatsink PGA with omni directional heatsink AIRFLOW ft min TEMPERATURE o C 0 100 200 300 400 500 600 700 800 120 115 110 105 100 95 90 PGA with uni directional heatsink ...

Page 39: ...gures 27 28 29 and 30 show the waveforms for various transactions on the 80960KB s local bus Figure 27 Non Burst Read and Write Transactions Without Wait States Ta Td Tr Ta Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 0 W R DT R DEN READY ...

Page 40: ...80960KB 34 Figure 28 Burst Read and Write Transaction Without Wait States Ta Td Td Tr Ta Td Td Td Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 0 W R DT R DEN READY ...

Page 41: ...80960KB 35 Figure 29 Burst Write Transaction with 2 1 1 1 Wait States Ta Tw Tw Td Tw Td Tw Td Tw Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 0 W R DT R DEN READY ...

Page 42: ...Figure 30 Accesses Generated by Quad Word Read Bus Request Misaligned Two Bytes from Quad Word Boundary 1 0 0 0 Wait States Ta Tw Td Td Td Td Tr Ta Tw Td Tr CLK2 CLK LAD31 0 ALE ADS BE3 2 W R DT R DEN READY BE1 0 ...

Page 43: ...NOTE INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1 For a second interrupt to be acknowledged INTR must be low for at least three cycles before it can be reasserted INTERRUPT ACKNOWLEDGEMENT CYCLE 1 IDLE 5 BUS STATES INTERRUPT ACKNOWLEDGEMENT CYCLE 2 PREVIOUS CYCLE ADDR VECTOR ADDR CLK ...

Page 44: ...ogy 2 7 DC Characteristics pg 15 005 ICC max specification reduced WAS IS AT 375 mA 315 mA 16 MHz 420 mA 360 mA 20 MHz 480 mA 420 mA 25 MHz Figures 7 8 9 23 24 25 and 26 have also been changed accordingly 2 8 AC Specifications pg 16 005 25 MHz operation extended to product in PQFP package T8 min improved at all frequencies from 0 ns to 2 ns and T8 max improved from 20 ns to 18 ns T8H max improveme...

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