background image

2

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR 

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS 

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING 

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, 

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for 

use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the 

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel 

or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL® PRE-RELEASE PRODUCTS.
Please review the terms at 

http://www.intel.com/netcomms/prerelease_terms.htm

 carefully before using any Intel® pre-release product, including any 

evaluation, development or reference hardware and/or software product (collectively, “Pre-Release Product”). By using the Pre-Release Product, you 

indicate your acceptance of these terms, which constitute the agreement (the “Agreement”) between you and Intel Corporation (“Intel”). In the event 

that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for 

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different 

processor families. See 

http://www.intel.com/products/processor_number

 for details.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not 

finalize a design with this information.

The I/O Control Hub (ICH8) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. 

Current characterized errata are available on request.
Hyper-Threading Technology requires a computer system with an Intel

®

 Pentium

®

 4 processor supporting HT Technology and a HT Technology enabled 

chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See

http://www.intel.com/

products/ht/Hyperthreading_more.htm

 for additional information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-

296-9333.
Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008, Intel Corporation. All Rights Reserved.

Summary of Contents for 8 LAN

Page 1: ...316234 006 Revision 2 8 Intel I O Controller Hub 8 LAN NVM Map and Information Guide January 2008...

Page 2: ...the Pre Release Product and promptly return it unused to Intel Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves th...

Page 3: ...17 Extended Configuration Word 2 Word 15h 14 1 4 18 Extended Configuration Word 3 Word 16h 14 1 4 19 LED 1 Configuration and Power Management Word 17h 15 1 4 20 LED 0 and 2 Configuration Defaults Word...

Page 4: ...13h to 0b 2 0 June 2006 Initial public release Added new LAN Word Offset 19h description to Tables 1 and 17 Added new EEPROM images to Appendix A Updated bit defaults and descriptions to Tables 9 10...

Page 5: ...lash device or devices along with the BIOS Manageability Firmware and a Flash Descriptor Region It is programmed through the ICH8 This combined image is shown in Figure 1 The Flash Descriptor Region i...

Page 6: ...l Intel representative 2 The GbE region must be part of the original image flashed onto the part 3 For Intel LAN tools and drivers to work correctly the BIOS must set the VSCC register s correctly Thi...

Page 7: ...IA address of the LAN controller In addition it also corrects the GbE component checksum field after the region is modified FTOOL does not have this ability For more information on how to use EEUPDATE...

Page 8: ...ved SW 0800h 04h 08 Reserved SW FFFFh 05h 0A Image Version Information 1 SW 06h 0Ch Reserved SW FFFFh 07h 0Eh Reserved SW FFFFh 08h 10h PBA Low SW 09h 12h PBA High SW 0Ah 14h PCI Initialization Contro...

Page 9: ...Register 0 RAL0 RAH0 The Intel default is listed in Table 2 Note The Ethernet IA is byte swapped as listed in Table 2 The IA bytes read from the NVM are used by the ICH8 until an IA Setup command is i...

Page 10: ...e driver should not rely on this field to identify the product or its capabilities Table 4 Reserved Word 04h Bit Name Default Description 15 0 Reserved FFFFh These bits are reserved and should be set...

Page 11: ...ary power indication It is used in conjunction with the PM Enable bit 0b D3cold wake up is not advertised 1b D3cold wake up is advertised in the PMC register of the PCI function if the PM Enable bit i...

Page 12: ...tform LAN Connect Device Bit Name Default Description 15 0 Reserved 00h Reserved Table 10 LAN Power Consumption Word 10h Bit Name Default Description 15 8 LAN D0 Power 0Dh for 82566 04h for 82562V The...

Page 13: ...wer down at DMoff D3 without Wake on LAN This bit is loaded to the PHY Power Down Enable bit in the CTRL_EXT register 8 Reserved 0b This bit is reserved and should be set to 0b 7 6 PHYT 00b This field...

Page 14: ...11 0 Extended Configuration Pointer 020h This field defines the base address in Dwords of the extended configuration area in the NVM It should equal a non zero value Table 13 Extended Configuration W...

Page 15: ...est speed supported by both link partners in all power states This bit enables a decrease in link speed in all power states 0b Low Power Link Up is disabled 1b Low Power Link Up is enabled in all powe...

Page 16: ...1b FULL_DUPLEX Asserted when the link is configured for full duplex operation 1010b COLLISION Asserted when a collision is observed 1011b ACTIVITY Asserted when link is established and packets are bei...

Page 17: ...GLOBAL_BLINK_MODE field in the LEDCTL register 4 Reserved 0b This bit is reserved and should be set to 0b 3 0 LED0 Mode 0100b These bits represent the initial value of the LED0_MODE field which specif...

Page 18: ...t to 1b and this bit is set to 0b indicates that both images are present in the Flash 14 EPB EFI Presence Setting this bit to 1b Indicates that the image in the Flash contains an EFI image Setting thi...

Page 19: ...ere is nothing in the agent to prevent their use on a NIC implementation 7 6 PT Prompt Time These bits control how long the Press Control S setup prompt message appears if enabled by DIM 00b 2 seconds...

Page 20: ...sumes the BIOS allows boot order setup for PnP Expansion ROMs and hooks interrupt 18h to inform the BIOS that the agent is a bootable device in addition to registering as a BBS IPL device The BIOS boo...

Page 21: ...low changes to the boot protocol 1 DTM Disable Title Message If set to 1b the title message displaying the version of the boot agent is suppressed the Control S message is also suppressed This is for...

Page 22: ...sum is incorrect and fix it in the image Note The default image always has a checksum value of 0 The default image always has a checksum value of 0b The LAD programming tools EEUPDATE or LANCONF updat...

Page 23: ...h Reserved 05h Image Version Information 1 06 07h Reserved 08 09h PBA Bytes 0Ah PCI Initialization Control Word 0Bh Subsystem ID 0Ch Subsystem Vendor ID 0Dh Device ID 0Eh Vendor ID 0Fh Device REV ID 1...

Page 24: ...4 0010 6120 001F 0E02 0012 2F40 001F 901B 001B 0000 0012 2FA0 001F F8F0 0012 2000 001F 10B0 0010 0000 0011 20C0 001F 249A 001D 00D3 001E 28A0 001F 04CE 0014 2F60 001F 29E4 0010 0000 001F 0140 0000 1F2...

Page 25: ...F FFFF Range 0x40 0x7F 6100 001F 0404 0010 6120 001F 0E02 0012 2F40 001F 9018 001B 0000 0012 2FA0 001F 8B24 0011 F8F0 0012 2000 001F 01B0 0010 0000 0011 20C0 001F 249A 001D 00D3 001E 28A0 001F 04CE 00...

Page 26: ...4 0010 6120 001F 0E02 0012 2F40 001F 9018 001B 0000 0012 2FA0 001F 8B24 0011 F8F0 0012 2000 001F 01B0 0010 0000 0011 20C0 001F 249A 001D 00D3 001E 28A0 001F 04CE 0014 2F60 001F 29E4 0010 0000 001F 014...

Page 27: ...000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 4000 121C 4007 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF Range 0x40 0x7F 0000 0000 0000 0000 0000 0000 0000 0000 0000...

Page 28: ...NVM Information Guide ICH8 28 Note This page intentionally left blank...

Reviews: