Intel 6300ESB ICH, Design Manual

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January 2007 147
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
The CPC signal routing shall transition from an external layer to an internal signal layer under the
GMCH. Keep the same internal layer until transitioning out to an external layer to connect to the
appropriate pad of the DIMM connector and the parallel termination resistor. When the layout
requires additional routing before the termination resistor, return to the same internal layer and
transition to an external layer immediately prior to parallel termination resistor.
External trace lengths shall be minimized. Intel suggests that the parallel termination be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external
signals shall be ground reference to keep the path of return current continuous. Intel suggests that
all control signals be routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) control termination resistors, but control signals
cannot be placed within the same R pack as the data or command signals. The table and diagrams
below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
control signals.
5.4.7.1 CPC Signal Routing Topology
Figure 73 depicts the CPC control signal routing topology.
The CPC signals shall be routed using 2:1 trace space to width ratio for signals within the DDR
group, except clocks and strobes. CPC signals shall be routed on inner layers with minimized
external trace lengths.
Figure 73. CPC Control Signal Routing Topology
P1
V tt
D IM M 0,1 PA D
w
R t
L2
M C H
P in
M C H
L 1