Intel 6300ESB ICH, Design Manual

Page: 107 / 320

January 2007 107
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
When the above criteria cannot be met by the system design, Table 23 must be adhered to during
power up. Refer to Intel
®
DDR 200 JEDEC Spec Addendum for more details.
4.8 Intel 855GME Chipset Platform Power Delivery
Guidelines
Each component is capable of generating large current swings when switching between logic high
and logic low. This condition could cause the component voltage rails to drop below specified
limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is
added in parallel to the voltage input pins. Intel recommends that the developer use the amount of
decoupling capacitors specified in this document to ensure the component maintains stable supply
voltages. The capacitors shall be placed as close to the package as possible. Rotate caps that sit
over power planes so that the loop inductance is minimized (see
Figure 51 ). The basic theory for
minimizing loop inductance is to consider which voltage is on Layer 2 (power or ground) and spin
the decoupling cap with the opposite voltage toward the ball grid array (BGA). This greatly
minimizes the total loop inductance. Intel recommends that for prototype board designs, the
designer shall include pads for extra power plane decoupling caps.
Table 23. DDR Power-Up Initialization Sequence
Voltage Description Sequencing Voltage Relationship to Avoid Latch-up
VDDQ After or with VDD
< VDD + 0.3 V
VTT After or with VDDQ
< VDDQ + 0.3 V
VREF After or with VDDQ
< VDDQ + 0.3 V
Figure 51. Example for Minimizing Loop Inductance
Layer 1
Layer 2
Layer 3
Layer 4
GND
GND
4.5 mils nominal
48 mils nominal
BGA
BALL
BGA
BALL
BGA
Substrate
PAD
Trace
connecting
Pad to Via
VIA
GND
Ball
PWR
Ball
Copper
Plane
Under BGA
Decoupling
Cap
PWR
Current Flow to Decoupling Cap