Intel 500 - DATASHEET REV 003, Datasheet

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Datasheet 55
Package Mechanical Specifications and Pin Information
DBR# Output
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
DEFER# Input
DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of both FSB agents.
DINV[3:0]#
Input/
Output
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals
are activated when the data on the data bus is inverted. The bus
agent inverts the data bus signals if more than half the bits, within
the covered group, would change level in the next cycle.
DPRSTP# Input
DPRSTP# is not used by the processor. For termination requirements
please refer to the platform design guide.
DPSLP# Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep state to the Deep Sleep state. In order to
return to the Sleep state, DPSLP# must be deasserted. DPSLP# is
driven by the Intel® ICH8M I/O controller.
DPWR# Input
DPWR# is a control signal used by the chipset to reduce power on
the processor data bus input buffers. This is not utilized by this
processor.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Table 15. Signal Description (Sheet 3 of 8)
Name Type Description
DINV[3:0]# Assignment to Data Bus
Bus Signal Data Bus Signals
DINV[3]# D[63:48]#
DINV[2]# D[47:32]#
DINV[1]# D[31:16]#
DINV[0]# D[15:0]#