DTM-5.9
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-4
Q202 : AK4388ET (192kHz 24-Bit 2ch DAC)
BLOCK DIAGRAM
PIN CONFIGURATION
TERMINAL DESCRIPTION
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
RSTN
Modulator
AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS
VCOM
De-emphasis
Control
Control
Port
Clock
Divider
DEM
SMUTE
ACKS
Modulator
8X
Interpolator
DZF
SCF
LPF
1
MCLK
LRCK
BICK
SMUTE
ACKS
DIF0
Top
View
2
3
4
5
6
7
8
DZF
DEM
VSS
VDD
VCOM
AOUTL
AOUTR
DIF1
16
15
14
13
12
11
10
9
RSTN
SDTI
No.
1
2
3
4
5
6
7
15
16
Pin Name
MCLK
BICK
SDTI
LRCK
RSTN
SMUTE
ACKS
DEM
DZF
I/O
I
I
I
I
I
I
I
I
I
O
O
O
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I
O
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
Audio Serial Data Clock pin
Audio Serial Data Input pin
L/R Clock Pin
Reset Mode Pin
When at “L”, the AK4388 is in the power- down mode and is held in reset.
The AK4388 should always be reset upon power-up.
Soft Mute Pin
“H” : Enable, “L” : Disable
Auto Setting Mode Pin
“L” : Manual Setting Mode, “H” : Auto Setting Mode
Audio Data Interface Format Pin
Audio Data Interface Format Pin (Internal pull-up pin)
Rch Analog Output Pin
Lch Analog Output Pin
Common Voltage Pin, VDD/2
Normally connected to VSS with a 10uF electrolytic cap.
Ground pin
Power supply Pin
De-emphasis Mode Pin (Internal pull-down pin)
When at “H”, the de-emphasis filter is available.
Zero Input Detect Pin
DIF0
DIF1
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