Integra DSR-4.8, Service Manual

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DSR-4.8
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
V
SS
DQ15 DQ14 V
SSQ
DQ13 DQ12 V
DDQ
DQ11 DQ10 V
SSQ
DQ9 DQ8 V
DDQ
N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 V
SS
V
DD
DQ0 DQ1
V
SSQ
DQ2 DQ3
V
DDQ
DQ4 DQ5
V
SSQ
DQ6 DQ7
V
DDQ
LDQM
WE
CAS RAS
CS BA
A10/AP
A0 A1 A2 A3
V
DD
PIN CONFIGURATION (Top View)
Q281 : SDRAM (M12L16161A)
CLK CKE CS RAS CAS WE L(U)DQM
Bank Select
CLK
ADD
Ad
dress Register
Ro
w Buff
er
Refresh Counter
LCBR LRAS
Ro
w Decoder
Col.
Buff
er
LCKE
LRAS LCBR LWE LCAS
Timing Register
LWCBR
LDQM
Programming Register
Latency & Burst Length
512K x 16
512K x 16
Sense AMP
Output Buff
er
DQi
LDQM
LWE
Data Input Register
I/O Contr
ol
Column Decoder
BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK
CS
CKE
A0 - A10/AP
BA
RAS
CAS
WE
L(U)DQM
System Xlock
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/ column addresses are multiplexed on the same pins.
Row address: RA0 - RA10. Column address : CA0 - CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE actuve.
Masks data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Chip Select
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION-5
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