Class
Port name
Function 1
Function 2
Function 3
I/O Description
I/O Descrition I/O Descrition
PORT ASSIGMENT-3
MBA[1]
O
SDRAM Bank Address
MD[0]
I/O SDRAM Data input/ output
MD[1]
I/O SDRAM Data input/ output
MD[2]
I/O SDRAM Data input/ output
MD[3]
I/O SDRAM Data input/ output
MD[4]
I/O SDRAM Data input/ output
MD[5]
I/O SDRAM Data input/ output
SDRAM I/F
MD[6]
I/O SDRAM Data input/ output
MD[7]
I/O SDRAM Data input/ output
MD[8]
I/O SDRAM Data input/ output
MD[9]
I/O SDRAM Data input/ output
MD[10]
I/O SDRAM Data input/ output
MD[11]
I/O SDRAM Data input/ output
MD[12]
I/O SDRAM Data input/ output
MD[13]
I/O SDRAM Data input/ output
MD[14]
I/O SDRAM Data input/ output
MD[15]
I/O SDRAM Data input/ output
BDREQ
O
Stream Request output pin
BDEN
I
Stream Enable input pin
BSECH
I
Sector display of head
BCLK
I
Stream data input pin
BD[0]
I
Stream data input pin
Stream I/F
BD[1]
I
Stream data input pin
BD[2]
I
Stream data input pin
I
Stream data input pin
I
Stream data input pin
I
Stream data input pin
I
Stream data input pin
I
Stream data input pin
CDNCK
I
CDDA Master clock input pin
I
CDDA Bit clock input pin
I
CDDA L/R clock input pin
CDDIN
I
CDDA PCM data input pin
CDDATA
I
CDDA Digital data input pin
DACCLK
O
Clock output pin for DAC
Audio I/F
DOCLK
O
Bit clock output pin for DAC
LRCLK
O
L/R clock output pin for DAC
AO0
O
Audio PCM output pin
AO1
O
Audio PCM output pin
AO2
O
Audio PCM output pin
AOD
O
Audio PCM output pin
DOUT0
O
Audio digital output pin
DOUT1
O
Audio digital output pin
DCS
O
SDRAM Chip select output pin
DCS2
O
SDRAM Chip select output pin
MCLK
O
SDRAM Clock output
RAS
O
SDARAM RAS output
CAS
O
SDARAM CAS output
DQML
O
SDARAM Data master
DQMU
O
SDARAM Data master
DWE
O
SDARAM Wright enable output
D
PC-7.5
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
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