Instruo eas Page 11 User Manual Download

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Patch Examples

Pulse Syncing:

Summary:

A primary use case for AND logic is to synchronize two

pulse signals. By connecting a steady clock signal to

AND Input 1

and

connecting a faster random pulse signal to

AND Input 2

, the

AND

Output

will generate random pulses only when the steady clock signal is

held HIGH.

Output

Steady Clock Signal

Random Clock Signal

Summary of Contents for eas

Page 1: ...eãs Logic Module User Manual ...

Page 2: ...tents 3 Description Features 4 Installation Specifications 5 Overview 6 Gate Logic 8 Boolean Logic Tables 10 Patch Examples Pulse Syncing Pulse Mixing Rhythmic Variations CMOS Style Ring Modulation Cheapnis ...

Page 5: ...or stream flows over a precipice or steep incline Key 1 AND Input 1 2 AND Input 2 3 AND Output 4 NAND Output 5 OR Input 1 6 OR Input 2 7 OR Output 8 NOR Output 9 XOR Input 1 10 XOR Input 2 1 1 XOR Output 12 XNOR Ouput 13 NOT Input 14 NOT Output 1 3 5 7 9 2 4 6 8 1 0 13 11 14 12 Normalisation ...

Page 7: ... XOR gate is present at the XNOR Output The NOR Output normals to XOR Input 2 NOT Gate Logic In NOT gate logic voltage is held HIGH at the output if LOW voltage is present at the input Similarly voltage is held LOW at the output if HIGH voltage is present at the input NOT gate logic is a way to invert gate and trigger signals The XOR Output normals to the NOT Input ...

Page 8: ...8 Boolean Logic Tables AND NAND Gate Logic 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 1 Input 1 Input 2 AND NAND ...

Page 9: ...9 OR NOR Gate Logic 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 1 Input 1 Input 2 OR NOR ...

Page 10: ...10 XOR XNOR Gate Logic NOT Gate Logic 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 Input 1 Input 2 XOR XNOR 0 1 1 0 Input NOT ...

Page 11: ...to synchronize two pulse signals By connecting a steady clock signal to AND Input 1 and connecting a faster random pulse signal to AND Input 2 the AND Output will generate random pulses only when the steady clock signal is held HIGH Output Steady Clock Signal Random Clock Signal ...

Page 12: ... is to mix two pulse signals By connecting a pulse signal to OR Input 1 and a different pulse signal to OR Input 2 the OR Output will generate a sum of the two pulse signals creating a more intricate pulse pattern Summed Output Clock Signal 1 Clock Signal 2 ...

Page 13: ... gates for interesting rhythmic outputs Experiment with different clock rates and logic gates Take advantage of the internal normalling and use three clock signals or gate trigger patterns instead of two Clock Signal 1 AND Output NAND Output OR Output NOR Output XOR Output XNOR Output NOT Output Clock Signal 3 Clock Signal 2 ...

Page 14: ...OR Inputs for CMOS style ring modulation effects This style of ring modulation is often used for synthesizing cymbal sounds It s also found on many classic synthesizers as a way to add overtones to the primary oscillator waveforms Output Output Audio Rate Signal 1 Audio Rate Signal 2 ...

Page 15: ...io rate signals at any of the logic gates for 1 bit pulse code modulation tones Unipolar positive audio rate signals will result in authentically cheap digital sounds Output Audio Rate Signal 3 Audio Rate Signal 2 Audio Rate Signal 1 ...

Page 16: ...16 This device meets the requirements of the following standards EN55032 EN55103 2 EN61000 3 2 EN61000 3 3 EN6231 1 Manual Author Collin Russell Manual Design Dominic D Sylva ...